Lines Matching +full:0 +full:x500

24 #define DMIC_INSTANCE			0x00
25 #define I2S_SP_INSTANCE			0x01
26 #define I2S_BT_INSTANCE			0x02
27 #define I2S_HS_INSTANCE			0x03
29 #define MEM_WINDOW_START		0x4080000
31 #define ACP_I2S_REG_START		0x1242400
32 #define ACP_I2S_REG_END			0x1242810
33 #define ACP3x_I2STDM_REG_START		0x1242400
34 #define ACP3x_I2STDM_REG_END		0x1242410
35 #define ACP3x_BT_TDM_REG_START		0x1242800
36 #define ACP3x_BT_TDM_REG_END		0x1242810
46 #define ACP_SRAM_SP_PB_PTE_OFFSET	0x0
47 #define ACP_SRAM_SP_CP_PTE_OFFSET	0x100
48 #define ACP_SRAM_BT_PB_PTE_OFFSET	0x200
49 #define ACP_SRAM_BT_CP_PTE_OFFSET	0x300
50 #define ACP_SRAM_PDM_PTE_OFFSET		0x400
51 #define ACP_SRAM_HS_PB_PTE_OFFSET       0x500
52 #define ACP_SRAM_HS_CP_PTE_OFFSET       0x600
53 #define PAGE_SIZE_4K_ENABLE		0x2
55 #define I2S_SP_TX_MEM_WINDOW_START	0x4000000
56 #define I2S_SP_RX_MEM_WINDOW_START	0x4020000
57 #define I2S_BT_TX_MEM_WINDOW_START	0x4040000
58 #define I2S_BT_RX_MEM_WINDOW_START	0x4060000
59 #define I2S_HS_TX_MEM_WINDOW_START      0x40A0000
60 #define I2S_HS_RX_MEM_WINDOW_START      0x40C0000
62 #define SP_PB_FIFO_ADDR_OFFSET		0x500
63 #define SP_CAPT_FIFO_ADDR_OFFSET	0x700
64 #define BT_PB_FIFO_ADDR_OFFSET		0x900
65 #define BT_CAPT_FIFO_ADDR_OFFSET	0xB00
66 #define HS_PB_FIFO_ADDR_OFFSET		0xD00
67 #define HS_CAPT_FIFO_ADDR_OFFSET	0xF00
79 #define FIFO_SIZE			0x100
80 #define DMA_SIZE			0x40
81 #define FRM_LEN				0x100
83 #define ACP3x_ITER_IRER_SAMP_LEN_MASK	0x38
88 #define TDM_DISABLE	0
90 #define SLOT_WIDTH_8	0x8
91 #define SLOT_WIDTH_16	0x10
92 #define SLOT_WIDTH_24	0x18
93 #define SLOT_WIDTH_32	0x20
176 	u64 byte_count, low = 0, high = 0;  in acp_get_byte_count()
245 	mclkgen.bits.i2stdm_master_mode = 0x1;  in acp_set_i2s_clk()
246 	mclkgen.bits.i2stdm_format_mode = 0x00;  in acp_set_i2s_clk()