56 #define SRC	regs[insn->src_reg]  macro
1684 		DST = DST OP (SRC & 63);		\  in ___bpf_prog_run()
1687 		DST = (u32) DST OP ((u32) SRC & 31);	\  in ___bpf_prog_run()
1698 		DST = DST OP SRC;			\  in ___bpf_prog_run()
1701 		DST = (u32) DST OP (u32) SRC;		\  in ___bpf_prog_run()
1726 		DST = (u32) SRC;  in ___bpf_prog_run()
1732 		DST = SRC;  in ___bpf_prog_run()
1742 		DST = (u64) (u32) (((s32) DST) >> (SRC & 31));  in ___bpf_prog_run()
1748 		(*(s64 *) &DST) >>= (SRC & 63);  in ___bpf_prog_run()
1754 		div64_u64_rem(DST, SRC, &AX);  in ___bpf_prog_run()
1759 		DST = do_div(AX, (u32) SRC);  in ___bpf_prog_run()
1770 		DST = div64_u64(DST, SRC);  in ___bpf_prog_run()
1774 		do_div(AX, (u32) SRC);  in ___bpf_prog_run()
1865 		if ((SIGN##64) DST CMP_OP (SIGN##64) SRC) {	\  in ___bpf_prog_run()
1871 		if ((SIGN##32) DST CMP_OP (SIGN##32) SRC) {	\  in ___bpf_prog_run()
1917 		*(SIZE *)(unsigned long) (DST + insn->off) = SRC;	\  in ___bpf_prog_run()
1923 		DST = *(SIZE *)(unsigned long) (SRC + insn->off);	\  in ___bpf_prog_run()
1927 				      (const void *)(long) (SRC + insn->off));	\  in ___bpf_prog_run()
1940 				atomic_##KOP((u32) SRC, (atomic_t *)(unsigned long) \  in ___bpf_prog_run()
1943 				atomic64_##KOP((u64) SRC, (atomic64_t *)(unsigned long) \  in ___bpf_prog_run()
1948 				SRC = (u32) atomic_fetch_##KOP(		\  in ___bpf_prog_run()
1949 					(u32) SRC,			\  in ___bpf_prog_run()
1952 				SRC = (u64) atomic64_fetch_##KOP(	\  in ___bpf_prog_run()
1953 					(u64) SRC,			\  in ___bpf_prog_run()
1968 				SRC = (u32) atomic_xchg(  in ___bpf_prog_run()
1970 					(u32) SRC);  in ___bpf_prog_run()
1972 				SRC = (u64) atomic64_xchg(  in ___bpf_prog_run()
1974 					(u64) SRC);  in ___bpf_prog_run()
1980 					(u32) BPF_R0, (u32) SRC);  in ___bpf_prog_run()
1984 					(u64) BPF_R0, (u64) SRC);  in ___bpf_prog_run()