Lines Matching +full:0 +full:x414

8 #define _LDDCKR			0x410
9 #define LDDCKR_ICKSEL_BUS	(0 << 16)
15 #define _LDDCKSTPR		0x414
16 #define _LDINTR			0x468
22 #define LDINTR_VES		(1 << 0)
23 #define LDINTR_STATUS_MASK	(0xff << 0)
24 #define _LDSR			0x46c
28 #define _LDCNT1R		0x470
29 #define LDCNT1R_DE		(1 << 0)
30 #define _LDCNT2R		0x474
35 #define LDCNT2R_DO		(1 << 0)
36 #define _LDRCNTR		0x478
40 #define LDRCNTR_MRC		(1 << 0)
41 #define _LDDDSR			0x47c
44 #define LDDDSR_BS		(1 << 0)
54 #define LDMT1R_MIFTYP_RGB8	(0x0 << 0)
55 #define LDMT1R_MIFTYP_RGB9	(0x4 << 0)
56 #define LDMT1R_MIFTYP_RGB12A	(0x5 << 0)
57 #define LDMT1R_MIFTYP_RGB12B	(0x6 << 0)
58 #define LDMT1R_MIFTYP_RGB16	(0x7 << 0)
59 #define LDMT1R_MIFTYP_RGB18	(0xa << 0)
60 #define LDMT1R_MIFTYP_RGB24	(0xb << 0)
61 #define LDMT1R_MIFTYP_YCBCR	(0xf << 0)
62 #define LDMT1R_MIFTYP_SYS8A	(0x0 << 0)
63 #define LDMT1R_MIFTYP_SYS8B	(0x1 << 0)
64 #define LDMT1R_MIFTYP_SYS8C	(0x2 << 0)
65 #define LDMT1R_MIFTYP_SYS8D	(0x3 << 0)
66 #define LDMT1R_MIFTYP_SYS9	(0x4 << 0)
67 #define LDMT1R_MIFTYP_SYS12	(0x5 << 0)
68 #define LDMT1R_MIFTYP_SYS16A	(0x7 << 0)
69 #define LDMT1R_MIFTYP_SYS16B	(0x8 << 0)
70 #define LDMT1R_MIFTYP_SYS16C	(0x9 << 0)
71 #define LDMT1R_MIFTYP_SYS18	(0xa << 0)
72 #define LDMT1R_MIFTYP_SYS24	(0xb << 0)
73 #define LDMT1R_MIFTYP_MASK	(0xf << 0)
78 #define LDDFR_YF_420		(0 << 8)
82 #define LDDFR_PKF_ARGB32	(0x00 << 0)
83 #define LDDFR_PKF_RGB16		(0x03 << 0)
84 #define LDDFR_PKF_RGB24		(0x0b << 0)
85 #define LDDFR_PKF_MASK		(0x1f << 0)
87 #define LDSM1R_OS		(1 << 0)
89 #define LDSM2R_OSTRG		(1 << 0)
91 #define LDPMR_LPS		(3 << 0)
93 #define _LDDWD0R		0x800
96 #define _LDDRDR			0x840
98 #define LDDRDR_DRD_MASK		(0x3ffff << 0)
99 #define _LDDWAR			0x900
100 #define LDDWAR_WA		(1 << 0)
101 #define _LDDRAR			0x904
102 #define LDDRAR_RA		(1 << 0)
126 enum { LCDC_CHAN_DISABLED = 0,
132 #define LCDC_FLAGS_DWPOL (1 << 0) /* Rising edge dot clock data latch */