Lines Matching +full:address +full:- +full:width
4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
47 #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
52 #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
55 #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
56 #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
57 #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
58 #define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */
59 #define S1DREG_LCD_MEM_OFF1 0x0047 /* LCD Memory Address Offset Register 1 */
63 #define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pi…
64 #define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */
66 #define S1DREG_CRT_HRTC_PWIDTH 0x0054 /* CRT/TV HRTC Pulse Width Register */
69 #define S1DREG_CRT_NDISP_VPER 0x0058 /* CRT/TV Vertical Non-Display Period Register */
71 #define S1DREG_CRT_VRTC_PWIDTH 0x005A /* CRT/TV VRTC Pulse Width Register */
74 #define S1DREG_CRT_DISP_START0 0x0062 /* CRT/TV Display Start Address Register 0 */
75 #define S1DREG_CRT_DISP_START1 0x0063 /* CRT/TV Display Start Address Register 1 */
76 #define S1DREG_CRT_DISP_START2 0x0064 /* CRT/TV Display Start Address Register 2 */
77 #define S1DREG_CRT_MEM_OFF0 0x0066 /* CRT/TV Memory Address Offset Register 0 */
78 #define S1DREG_CRT_MEM_OFF1 0x0067 /* CRT/TV Memory Address Offset Register 1 */
83 #define S1DREG_LCD_CUR_START 0x0071 /* LCD Ink/Cursor Start Address Register */
96 #define S1DREG_CRT_CUR_START 0x0081 /* CRT/TV Ink/Cursor Start Address Register */
112 #define S1DREG_BBLT_SRC_START0 0x0104 /* BitBLT Source Start Address Register 0 */
113 #define S1DREG_BBLT_SRC_START1 0x0105 /* BitBLT Source Start Address Register 1 */
114 #define S1DREG_BBLT_SRC_START2 0x0106 /* BitBLT Source Start Address Register 2 */
115 #define S1DREG_BBLT_DST_START0 0x0108 /* BitBLT Destination Start Address Register 0 */
116 #define S1DREG_BBLT_DST_START1 0x0109 /* BitBLT Destination Start Address Register 1 */
117 #define S1DREG_BBLT_DST_START2 0x010A /* BitBLT Destination Start Address Register 2 */
118 #define S1DREG_BBLT_MEM_OFF0 0x010C /* BitBLT Memory Address Offset Register 0 */
119 #define S1DREG_BBLT_MEM_OFF1 0x010D /* BitBLT Memory Address Offset Register 1 */
120 #define S1DREG_BBLT_WIDTH0 0x0110 /* BitBLT Width Register 0 */
121 #define S1DREG_BBLT_WIDTH1 0x0111 /* BitBLT Width Register 1 */
128 #define S1DREG_LKUP_MODE 0x01E0 /* Look-Up Table Mode Register */
129 #define S1DREG_LKUP_ADDR 0x01E2 /* Look-Up Table Address Register */
130 #define S1DREG_LKUP_DATA 0x01E4 /* Look-Up Table Data Register */
133 #define S1DREG_CPU2MEM_WDOGT 0x01F4 /* CPU-to-Memory Access Watchdog Timer Register */