Lines Matching full:1600
705 V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
714 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
722 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
730 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
738 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
746 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
754 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
915 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
923 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
930 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
937 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
944 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \