Lines Matching full:1200
714 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
722 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
730 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
738 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
746 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
754 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
847 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
855 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
862 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
869 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
876 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \