Lines Matching +full:0 +full:x800e0000

14 	IDXD_SCMD_DEV_ENABLED = 0x80000010,
15 	IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020,
16 	IDXD_SCMD_WQ_ENABLED = 0x80000021,
17 	IDXD_SCMD_DEV_DMA_ERR = 0x80020000,
18 	IDXD_SCMD_WQ_NO_GRP = 0x80030000,
19 	IDXD_SCMD_WQ_NO_NAME = 0x80040000,
20 	IDXD_SCMD_WQ_NO_SVM = 0x80050000,
21 	IDXD_SCMD_WQ_NO_THRESH = 0x80060000,
22 	IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000,
23 	IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000,
24 	IDXD_SCMD_PERCPU_ERR = 0x80090000,
25 	IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000,
26 	IDXD_SCMD_CDEV_ERR = 0x800b0000,
27 	IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000,
28 	IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000,
29 	IDXD_SCMD_WQ_NO_SIZE = 0x800e0000,
30 	IDXD_SCMD_WQ_NO_PRIV = 0x800f0000,
31 	IDXD_SCMD_WQ_IRQ_ERR = 0x80100000,
32 	IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000,
35 #define IDXD_SCMD_SOFTERR_MASK	0x80000000
39 #define IDXD_OP_FLAG_FENCE	0x0001
40 #define IDXD_OP_FLAG_BOF	0x0002
41 #define IDXD_OP_FLAG_CRAV	0x0004
42 #define IDXD_OP_FLAG_RCR	0x0008
43 #define IDXD_OP_FLAG_RCI	0x0010
44 #define IDXD_OP_FLAG_CRSTS	0x0020
45 #define IDXD_OP_FLAG_CR		0x0080
46 #define IDXD_OP_FLAG_CC		0x0100
47 #define IDXD_OP_FLAG_ADDR1_TCS	0x0200
48 #define IDXD_OP_FLAG_ADDR2_TCS	0x0400
49 #define IDXD_OP_FLAG_ADDR3_TCS	0x0800
50 #define IDXD_OP_FLAG_CR_TCS	0x1000
51 #define IDXD_OP_FLAG_STORD	0x2000
52 #define IDXD_OP_FLAG_DRDBK	0x4000
53 #define IDXD_OP_FLAG_DSTS	0x8000
56 #define IDXD_OP_FLAG_RD_SRC2_AECS	0x010000
57 #define IDXD_OP_FLAG_RD_SRC2_2ND	0x020000
58 #define IDXD_OP_FLAG_WR_SRC2_AECS_COMP	0x040000
59 #define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL	0x080000
60 #define IDXD_OP_FLAG_SRC2_STS		0x100000
61 #define IDXD_OP_FLAG_CRC_RFC3720	0x200000
65 	DSA_OPCODE_NOOP = 0,
75 	DSA_OPCODE_CRCGEN = 0x10,
81 	DSA_OPCODE_CFLUSH = 0x20,
85 	IAX_OPCODE_NOOP = 0,
88 	IAX_OPCODE_DECOMPRESS = 0x42,
91 	IAX_OPCODE_ZERO_DECOMP_32 = 0x48,
93 	IAX_OPCODE_ZERO_COMP_32 = 0x4c,
95 	IAX_OPCODE_SCAN = 0x50,
106 	DSA_COMP_NONE = 0,
116 	DSA_COMP_BAD_OPCODE = 0x10,
138 	IAX_COMP_NONE = 0,
140 	IAX_COMP_PAGE_FAULT_IR = 0x04,
141 	IAX_COMP_ANALYTICS_ERROR = 0x0a,
143 	IAX_COMP_BAD_OPCODE = 0x10,
147 	IAX_COMP_OVERLAP_BUFFERS = 0x16,
148 	IAX_COMP_INT_HANDLE_INVAL = 0x19,
160 	IAX_COMP_INVALID_COMP_FLAG = 0x30,
168 #define DSA_COMP_STATUS_MASK		0x7f
169 #define DSA_COMP_STATUS_WRITE		0x80