Lines Matching +full:non +full:- +full:linear
39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
210 * IEEE 754-2008 binary16 half-precision float
220 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
236 …10 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
240 * 16-xx padding occupy lsb
248 * 16-xx padding occupy lsb except Y410
273 * 1-plane YUV 4:2:0
275 * then V), but the exact Linear layout is undefined.
276 * These formats can only be used with a non-Linear modifier.
283 * index 0 = RGB plane, same format as the corresponding non _A8 format has
306 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
307 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
350 /* 3 plane non-subsampled (444) YCbCr
358 /* 3 plane non-subsampled (444) YCrCb
383 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) plane…
384 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) plane…
390 * Format modifiers describe, typically, a re-ordering or modification
394 * The upper 8 bits of the format modifier are a vendor-id as assigned
413 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
433 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
435 * compatibility, in cases where a vendor-specific definition already exists and
440 * generic layouts (such as pixel re-ordering), which may have
441 * independently-developed support across multiple vendors.
444 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
467 * Linear Layout
469 * Just plain linear layout. Note that this is different from no specifying any
471 * which tells the driver to also take driver-internal information into account
480 * implicit, instead it means that the layout is linear. Whether modifiers are
481 * used is out-of-band information carried in an API-specific way (e.g. in a
489 * Intel X-tiling layout
492 * in row-major layout. Within the tile bytes are laid out row-major, with
493 * a platform-dependent stride. On top of that the memory can apply
494 * platform-depending swizzling of some higher address bits into bit6.
498 * cross-driver sharing. It exists since on a given platform it does uniquely
499 * identify the layout in a simple way for i915-specific userspace, which
506 * Intel Y-tiling layout
509 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
510 * chunks column-major, with a platform-dependent height. On top of that the
511 * memory can apply platform-depending swizzling of some higher address bits
516 * cross-driver sharing. It exists since on a given platform it does uniquely
517 * identify the layout in a simple way for i915-specific userspace, which
524 * Intel Yf-tiling layout
526 * This is a tiled layout using 4Kb tiles in row-major layout.
527 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
528 * are arranged in four groups (two wide, two high) with column-major layout.
530 * out as 2x2 column-major.
542 * The main surface will be plane index 0 and must be Y/Yf-tiled,
559 * Intel color control surfaces (CCS) for Gen-12 render compression.
561 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
565 * Y-tile widths.
570 * Intel color control surfaces (CCS) for Gen-12 media compression
572 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
576 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
583 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
586 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
604 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
625 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
649 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
651 * Macroblocks are laid in a Z-shape, and each pixel data is following the
656 * - multiple of 128 pixels for the width
657 * - multiple of 32 pixels for the height
659 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
664 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
666 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
676 * Implementation may be platform and base-format specific.
689 * Implementation may be platform and base-format specific.
702 * Implementation may be platform and base-format specific.
712 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
718 * Vivante 64x64 super-tiling layout
720 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
721 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
725 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
730 * Vivante 4x4 tiling layout for dual-pipe
734 * compared to the non-split tiled layout.
739 * Vivante 64x64 super-tiling layout for dual-pipe
741 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
743 * therefore halved compared to the non-split super-tiled layout.
757 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
771 * ---- ----- -----------------------------------------------------------------
775 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
777 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
779 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
781 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
789 * 11:9 - Reserved (To support 2D-array textures with variable array stride
810 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
811 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
817 * page kind and block linear swizzles. This causes the layout of
821 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
837 * 55:25 - Reserved for future use. Must be zero.
847 /* To grandfather in prior block linear format modifiers to the above layout,
848 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
849 * with block-linear layouts, is remapped within drivers to the value 0xfe,
850 * which corresponds to the "generic" kind used for simple single-sample
851 * uncompressed color formats on Fermi - Volta GPUs.
863 * 16Bx2 Block Linear layout, used by Tegra K1 and later
868 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
911 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
913 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
920 * can't do linear). The T format has:
922 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
925 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
928 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
932 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
933 * tiles) or right-to-left (odd rows of 4k tiles).
956 * and UV. Some SAND-using hardware stores UV in a separate tiled
1000 * the assumption is that a no-XOR tiling modifier will be created.
1008 * It provides fine-grained random access and minimizes the amount of data
1013 * and different devices or use-cases may support different combinations.
1045 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1062 * AFBC block-split
1083 * AFBC copy-block restrict
1085 * Buffers with this flag must obey the copy-block restriction. The restriction
1086 * is such that there are no copy-blocks referring across the border of 8x8
1106 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1112 * AFBC double-buffer
1114 * Indicates that the buffer is allocated in a layout safe for front-buffer
1122 * Indicates that the buffer includes per-superblock content hints.
1139 * Arm Fixed-Rate Compression (AFRC) modifiers
1143 * reductions in graphics and media use-cases.
1159 * ---------------- ---------------
1170 * ------ ----------------- ------------------
1179 * ----------------------------- --------- ----------------- ------------------
1182 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1183 * ----------------------------- --------- ----------------- ------------------
1186 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1187 * ----------------------------- --------- ----------------- ------------------
1189 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1190 * ----------------------------- --------- ----------------- ------------------
1193 * ----------------------------- --------- ----------------- ------------------
1212 * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1217 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1219 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1221 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1235 * Indicates if the buffer uses the scanline-optimised layout
1236 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1242 * Arm 16x16 Block U-Interleaved modifier
1260 * The pixel order in each tile is linear and the tiles are disposed linearly,
1261 * both in row-major order.
1275 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1277 * - DRM_FORMAT_YUV420_8BIT
1278 * - DRM_FORMAT_YUV420_10BIT
1302 * - a body content organized in 64x32 superblocks with 4096 bytes per
1304 * - a 32 bytes per 128x64 header block
1322 * be accessible by the user-space clients, but only accessible by the
1325 * The user-space clients should expect a failure while trying to mmap
1326 * the DMA-BUF handle returned by the producer.
1351 * - main surface
1354 * - main surface in plane 0
1355 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1358 * - main surface in plane 0
1359 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1360 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1362 * For multi-plane formats the above surfaces get merged into one plane for
1366 * ----- ------------------------ ---------------------------------------------
1382 * 55:36 - Reserved for future use, must be zero
1401 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1425 * one which is not-aligned.