Lines Matching full:layout
46 * format and data layout of the buffer, and should be the only way to describe
49 * Having multiple fourcc:modifier pairs which describe the same layout should
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
275 * then V), but the exact Linear layout is undefined.
427 * When adding a new token please document the layout with a code comment,
443 * In future cases where a generic layout is identified before merging with a
467 * Linear Layout
469 * Just plain linear layout. Note that this is different from no specifying any
480 * implicit, instead it means that the layout is linear. Whether modifiers are
489 * Intel X-tiling layout
491 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
492 * in row-major layout. Within the tile bytes are laid out row-major, with
496 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
499 * identify the layout in a simple way for i915-specific userspace, which
506 * Intel Y-tiling layout
508 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
509 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
514 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
517 * identify the layout in a simple way for i915-specific userspace, which
524 * Intel Yf-tiling layout
526 * This is a tiled layout using 4Kb tiles in row-major layout.
528 * are arranged in four groups (two wide, two high) with column-major layout.
602 * Intel Tile 4 layout
604 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
666 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
667 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
710 * Vivante 4x4 tiling layout
712 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
713 * layout.
718 * Vivante 64x64 super-tiling layout
720 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
722 * major layout.
730 * Vivante 4x4 tiling layout for dual-pipe
732 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
734 * compared to the non-split tiled layout.
739 * Vivante 64x64 super-tiling layout for dual-pipe
741 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
743 * therefore halved compared to the non-split super-tiled layout.
750 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
757 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
760 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
777 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
794 * tables of all GPUs >= NV50. It affects the exact layout of bits
802 * since the modifier should define the layout of the associated
808 * kind and bit layout has changed at various points.
815 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
817 * page kind and block linear swizzles. This causes the layout of
821 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
822 * 1 = Desktop GPU and Tegra Xavier+ Layout
827 * 1 = ROP/3D, layout 1, exact compression format implied by Page
829 * 2 = ROP/3D, layout 2, exact compression format implied by Page
847 /* To grandfather in prior block linear format modifiers to the above layout,
863 * 16Bx2 Block Linear layout, used by Tegra K1 and later
919 * This is the primary layout that the V3D GPU can texture from (it
1071 * AFBC sparse layout
1092 * AFBC tiled layout
1094 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1098 * When the tiled layout is used, the buffer size (in pixels) must be aligned
1114 * Indicates that the buffer is allocated in a layout safe for front-buffer
1131 * The buffer layout is the same as for AFBC buffers without USM set, this only
1167 * scanline (SCAN layout) or rotated (ROT layout) access.
1169 * Layout Paging Tile Width Paging Tile Height
1176 * scanline (SCAN layout) or rotated (ROT layout) access.
1178 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height
1233 * AFRC scanline memory layout.
1235 * Indicates if the buffer uses the scanline-optimised layout
1236 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1237 * The memory layout is the same for all planes.
1280 * The first 8 bits of the mode defines the layout, then the following 8 bits
1281 * defines the options changing the layout.
1284 * combinations of layout and options.
1299 * Amlogic FBC Basic Layout
1301 * The basic layout is composed of:
1306 * This layout is transferrable between Amlogic SoCs supporting this modifier.
1311 * Amlogic FBC Scatter Memory layout
1314 * frames content to optimize memory access and layout.
1321 * Due to the nature of the layout, these buffers are not expected to
1330 /* Amlogic FBC Layout Options Bit Mask */
1339 * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1340 * the basic layout and 3200 bytes per 64x32 superblock combined with
1341 * the scatter layout.
1348 * Memory layout: