Lines Matching +full:max +full:- +full:bit +full:- +full:rate

1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
40 #define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE		BIT(0)
42 #define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE		BIT(1)
44 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA		BIT(2)
46 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA		BIT(3)
48 #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA			BIT(4)
50 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH	BIT(5)
52 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES               BIT(6)
54 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES               BIT(7)
56 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_AON		BIT(8)
58 /* DMIC max. four controllers for eight microphone channels */
61 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
93 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
97 	uint32_t rate;  member
101 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */
105 	uint32_t rate;  member
112 /* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */
126  * 3. If PDM bit errors are seen in capture (poor quality) the skew parameter
155  * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are
156  * multi-mode capable and there may be denied mic clock frequencies between
158  * avoid the driver to set clock to an illegal rate.
160  * The duty cycle could be set to 48-52% if not known. Generally these
164  * The microphone clock needs to be usually about 50-80 times the used audio
165  * sample rate. With highest sample rates above 48 kHz this can relaxed
183 	uint32_t fifo_fs;	/**< FIFO sample rate in Hz (8000..96000) */
189 	uint16_t duty_max;	/**< Max. mic clock duty cycle in % (min..80) */