Lines Matching +full:32 +full:khz

29 #define MAXPAGES0       4096	/* 32 bit mode */
39 #define AUDIGY_DMA_MASK		0xffffffffUL	/* 32bit mode */
178 #define HCFG_BAUD_RATE		0x00080000	/* 0 = 48kHz, 1 = 44.1kHz			*/
179 #define HCFG_EXPANDED_MEM	0x00040000	/* 1 = any 16M of 4G addr, 0 = 32M of 2G addr	*/
587 #define ADCCR_SAMPLERATE_48	0x00000000	/* 48kHz sample rate					*/
588 #define ADCCR_SAMPLERATE_44	0x00000001	/* 44.1kHz sample rate					*/
589 #define ADCCR_SAMPLERATE_32	0x00000002	/* 32kHz sample rate					*/
590 #define ADCCR_SAMPLERATE_24	0x00000003	/* 24kHz sample rate					*/
591 #define ADCCR_SAMPLERATE_22	0x00000004	/* 22.05kHz sample rate					*/
592 #define ADCCR_SAMPLERATE_16	0x00000005	/* 16kHz sample rate					*/
593 #define ADCCR_SAMPLERATE_11	0x00000006	/* 11.025kHz sample rate				*/
594 #define ADCCR_SAMPLERATE_8	0x00000007	/* 8kHz sample rate					*/
595 #define A_ADCCR_SAMPLERATE_12	0x00000006	/* 12kHz sample rate					*/
596 #define A_ADCCR_SAMPLERATE_11	0x00000007	/* 11.025kHz sample rate				*/
597 #define A_ADCCR_SAMPLERATE_8	0x00000008	/* 8kHz sample rate					*/
603 						/* is 16bit, 48KHz only. All 32 channels can be enabled */
729 #define SPCS_SAMPLERATE_44	0x00000000	/* 44.1kHz sample rate				*/
730 #define SPCS_SAMPLERATE_48	0x02000000	/* 48kHz sample rate				*/
731 #define SPCS_SAMPLERATE_32	0x03000000	/* 32kHz sample rate				*/
750 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status      		*/
816 /* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status      		*/
849 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) 		*/
913 /* Each FX general purpose register is 32 bits in length, all bits are used			*/
921 /* decompressed back to 20 bits on a read.  There are a total of 160 locations, the last 32	*/
926 /* Combined address field and memory opcode or flag field.  160 locations, last 32 are external	*/
1024 #define EMU_HANA_DOCK_LEDS_2_44K	0x01	/* 44.1 kHz LED on */
1025 #define EMU_HANA_DOCK_LEDS_2_48K	0x02	/* 48 kHz LED on */
1026 #define EMU_HANA_DOCK_LEDS_2_96K	0x04	/* 96 kHz LED on */
1027 #define EMU_HANA_DOCK_LEDS_2_192K	0x08	/* 192 kHz LED on */
1050 #define EMU_HANA_DOCK_PHONES_192_DAC1	0x00	/* DAC 1 Headphones source at 192kHz */
1051 #define EMU_HANA_DOCK_PHONES_192_DAC2	0x10	/* DAC 2 Headphones source at 192kHz */
1052 #define EMU_HANA_DOCK_PHONES_192_DAC3	0x20	/* DAC 3 Headphones source at 192kHz */
1053 #define EMU_HANA_DOCK_PHONES_192_DAC4	0x30	/* DAC 4 Headphones source at 192kHz */
1113  * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1115  * 0x01, 0x10-0x1f: 32 Elink channels to Audio Dock
1144  * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1146  * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1165  * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1175  * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1185  * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1187  * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1205 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1209 /* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */
1231 #define EMU_DST_DOCK_DAC1_LEFT1	0x0100	/* Audio Dock DAC1 Left, 1st or 48kHz only */
1232 #define EMU_DST_DOCK_DAC1_LEFT2	0x0101	/* Audio Dock DAC1 Left, 2nd or 96kHz */
1233 #define EMU_DST_DOCK_DAC1_LEFT3	0x0102	/* Audio Dock DAC1 Left, 3rd or 192kHz */
1234 #define EMU_DST_DOCK_DAC1_LEFT4	0x0103	/* Audio Dock DAC1 Left, 4th or 192kHz */
1235 #define EMU_DST_DOCK_DAC1_RIGHT1	0x0104	/* Audio Dock DAC1 Right, 1st or 48kHz only */
1236 #define EMU_DST_DOCK_DAC1_RIGHT2	0x0105	/* Audio Dock DAC1 Right, 2nd or 96kHz */
1237 #define EMU_DST_DOCK_DAC1_RIGHT3	0x0106	/* Audio Dock DAC1 Right, 3rd or 192kHz */
1238 #define EMU_DST_DOCK_DAC1_RIGHT4	0x0107	/* Audio Dock DAC1 Right, 4th or 192kHz */
1239 #define EMU_DST_DOCK_DAC2_LEFT1	0x0108	/* Audio Dock DAC2 Left, 1st or 48kHz only */
1240 #define EMU_DST_DOCK_DAC2_LEFT2	0x0109	/* Audio Dock DAC2 Left, 2nd or 96kHz */
1241 #define EMU_DST_DOCK_DAC2_LEFT3	0x010a	/* Audio Dock DAC2 Left, 3rd or 192kHz */
1242 #define EMU_DST_DOCK_DAC2_LEFT4	0x010b	/* Audio Dock DAC2 Left, 4th or 192kHz */
1243 #define EMU_DST_DOCK_DAC2_RIGHT1	0x010c	/* Audio Dock DAC2 Right, 1st or 48kHz only */
1244 #define EMU_DST_DOCK_DAC2_RIGHT2	0x010d	/* Audio Dock DAC2 Right, 2nd or 96kHz */
1245 #define EMU_DST_DOCK_DAC2_RIGHT3	0x010e	/* Audio Dock DAC2 Right, 3rd or 192kHz */
1246 #define EMU_DST_DOCK_DAC2_RIGHT4	0x010f	/* Audio Dock DAC2 Right, 4th or 192kHz */
1247 #define EMU_DST_DOCK_DAC3_LEFT1	0x0110	/* Audio Dock DAC1 Left, 1st or 48kHz only */
1248 #define EMU_DST_DOCK_DAC3_LEFT2	0x0111	/* Audio Dock DAC1 Left, 2nd or 96kHz */
1249 #define EMU_DST_DOCK_DAC3_LEFT3	0x0112	/* Audio Dock DAC1 Left, 3rd or 192kHz */
1250 #define EMU_DST_DOCK_DAC3_LEFT4	0x0113	/* Audio Dock DAC1 Left, 4th or 192kHz */
1251 #define EMU_DST_DOCK_PHONES_LEFT1	0x0112	/* Audio Dock PHONES Left, 1st or 48kHz only */
1252 #define EMU_DST_DOCK_PHONES_LEFT2	0x0113	/* Audio Dock PHONES Left, 2nd or 96kHz */
1253 #define EMU_DST_DOCK_DAC3_RIGHT1	0x0114	/* Audio Dock DAC1 Right, 1st or 48kHz only */
1254 #define EMU_DST_DOCK_DAC3_RIGHT2	0x0115	/* Audio Dock DAC1 Right, 2nd or 96kHz */
1255 #define EMU_DST_DOCK_DAC3_RIGHT3	0x0116	/* Audio Dock DAC1 Right, 3rd or 192kHz */
1256 #define EMU_DST_DOCK_DAC3_RIGHT4	0x0117	/* Audio Dock DAC1 Right, 4th or 192kHz */
1257 #define EMU_DST_DOCK_PHONES_RIGHT1	0x0116	/* Audio Dock PHONES Right, 1st or 48kHz only */
1258 #define EMU_DST_DOCK_PHONES_RIGHT2	0x0117	/* Audio Dock PHONES Right, 2nd or 96kHz */
1259 #define EMU_DST_DOCK_DAC4_LEFT1	0x0118	/* Audio Dock DAC2 Left, 1st or 48kHz only */
1260 #define EMU_DST_DOCK_DAC4_LEFT2	0x0119	/* Audio Dock DAC2 Left, 2nd or 96kHz */
1261 #define EMU_DST_DOCK_DAC4_LEFT3	0x011a	/* Audio Dock DAC2 Left, 3rd or 192kHz */
1262 #define EMU_DST_DOCK_DAC4_LEFT4	0x011b	/* Audio Dock DAC2 Left, 4th or 192kHz */
1263 #define EMU_DST_DOCK_SPDIF_LEFT1	0x011a	/* Audio Dock SPDIF Left, 1st or 48kHz only */
1264 #define EMU_DST_DOCK_SPDIF_LEFT2	0x011b	/* Audio Dock SPDIF Left, 2nd or 96kHz */
1265 #define EMU_DST_DOCK_DAC4_RIGHT1	0x011c	/* Audio Dock DAC2 Right, 1st or 48kHz only */
1266 #define EMU_DST_DOCK_DAC4_RIGHT2	0x011d	/* Audio Dock DAC2 Right, 2nd or 96kHz */
1267 #define EMU_DST_DOCK_DAC4_RIGHT3	0x011e	/* Audio Dock DAC2 Right, 3rd or 192kHz */
1268 #define EMU_DST_DOCK_DAC4_RIGHT4	0x011f	/* Audio Dock DAC2 Right, 4th or 192kHz */
1269 #define EMU_DST_DOCK_SPDIF_RIGHT1	0x011e	/* Audio Dock SPDIF Right, 1st or 48kHz only */
1270 #define EMU_DST_DOCK_SPDIF_RIGHT2	0x011f	/* Audio Dock SPDIF Right, 2nd or 96kHz */
1271 #define EMU_DST_HANA_SPDIF_LEFT1	0x0200	/* Hana SPDIF Left, 1st or 48kHz only */
1272 #define EMU_DST_HANA_SPDIF_LEFT2	0x0202	/* Hana SPDIF Left, 2nd or 96kHz */
1273 #define EMU_DST_HANA_SPDIF_RIGHT1	0x0201	/* Hana SPDIF Right, 1st or 48kHz only */
1274 #define EMU_DST_HANA_SPDIF_RIGHT2	0x0203	/* Hana SPDIF Right, 2nd or 96kHz */
1275 #define EMU_DST_HAMOA_DAC_LEFT1	0x0300	/* Hamoa DAC Left, 1st or 48kHz only */
1276 #define EMU_DST_HAMOA_DAC_LEFT2	0x0302	/* Hamoa DAC Left, 2nd or 96kHz */
1277 #define EMU_DST_HAMOA_DAC_LEFT3	0x0304	/* Hamoa DAC Left, 3rd or 192kHz */
1278 #define EMU_DST_HAMOA_DAC_LEFT4	0x0306	/* Hamoa DAC Left, 4th or 192kHz */
1279 #define EMU_DST_HAMOA_DAC_RIGHT1	0x0301	/* Hamoa DAC Right, 1st or 48kHz only */
1280 #define EMU_DST_HAMOA_DAC_RIGHT2	0x0303	/* Hamoa DAC Right, 2nd or 96kHz */
1281 #define EMU_DST_HAMOA_DAC_RIGHT3	0x0305	/* Hamoa DAC Right, 3rd or 192kHz */
1282 #define EMU_DST_HAMOA_DAC_RIGHT4	0x0307	/* Hamoa DAC Right, 4th or 192kHz */
1292 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */
1294 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */
1296 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */
1298 /* Microdock S/PDIF OUT Right, 2nd or 96kHz  */
1303 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1305 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1312  * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1314  * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1336  * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1338  * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1360  * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1373  * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1386  * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1388  * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1407 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1414 #define EMU_SRC_DOCK_MIC_A1	0x0100	/* Audio Dock Mic A, 1st or 48kHz only */
1415 #define EMU_SRC_DOCK_MIC_A2	0x0101	/* Audio Dock Mic A, 2nd or 96kHz */
1416 #define EMU_SRC_DOCK_MIC_A3	0x0102	/* Audio Dock Mic A, 3rd or 192kHz */
1417 #define EMU_SRC_DOCK_MIC_A4	0x0103	/* Audio Dock Mic A, 4th or 192kHz */
1418 #define EMU_SRC_DOCK_MIC_B1	0x0104	/* Audio Dock Mic B, 1st or 48kHz only */
1419 #define EMU_SRC_DOCK_MIC_B2	0x0105	/* Audio Dock Mic B, 2nd or 96kHz */
1420 #define EMU_SRC_DOCK_MIC_B3	0x0106	/* Audio Dock Mic B, 3rd or 192kHz */
1421 #define EMU_SRC_DOCK_MIC_B4	0x0107	/* Audio Dock Mic B, 4th or 192kHz */
1422 #define EMU_SRC_DOCK_ADC1_LEFT1	0x0108	/* Audio Dock ADC1 Left, 1st or 48kHz only */
1423 #define EMU_SRC_DOCK_ADC1_LEFT2	0x0109	/* Audio Dock ADC1 Left, 2nd or 96kHz */
1424 #define EMU_SRC_DOCK_ADC1_LEFT3	0x010a	/* Audio Dock ADC1 Left, 3rd or 192kHz */
1425 #define EMU_SRC_DOCK_ADC1_LEFT4	0x010b	/* Audio Dock ADC1 Left, 4th or 192kHz */
1426 #define EMU_SRC_DOCK_ADC1_RIGHT1	0x010c	/* Audio Dock ADC1 Right, 1st or 48kHz only */
1427 #define EMU_SRC_DOCK_ADC1_RIGHT2	0x010d	/* Audio Dock ADC1 Right, 2nd or 96kHz */
1428 #define EMU_SRC_DOCK_ADC1_RIGHT3	0x010e	/* Audio Dock ADC1 Right, 3rd or 192kHz */
1429 #define EMU_SRC_DOCK_ADC1_RIGHT4	0x010f	/* Audio Dock ADC1 Right, 4th or 192kHz */
1430 #define EMU_SRC_DOCK_ADC2_LEFT1	0x0110	/* Audio Dock ADC2 Left, 1st or 48kHz only */
1431 #define EMU_SRC_DOCK_ADC2_LEFT2	0x0111	/* Audio Dock ADC2 Left, 2nd or 96kHz */
1432 #define EMU_SRC_DOCK_ADC2_LEFT3	0x0112	/* Audio Dock ADC2 Left, 3rd or 192kHz */
1433 #define EMU_SRC_DOCK_ADC2_LEFT4	0x0113	/* Audio Dock ADC2 Left, 4th or 192kHz */
1434 #define EMU_SRC_DOCK_ADC2_RIGHT1	0x0114	/* Audio Dock ADC2 Right, 1st or 48kHz only */
1435 #define EMU_SRC_DOCK_ADC2_RIGHT2	0x0115	/* Audio Dock ADC2 Right, 2nd or 96kHz */
1436 #define EMU_SRC_DOCK_ADC2_RIGHT3	0x0116	/* Audio Dock ADC2 Right, 3rd or 192kHz */
1437 #define EMU_SRC_DOCK_ADC2_RIGHT4	0x0117	/* Audio Dock ADC2 Right, 4th or 192kHz */
1438 #define EMU_SRC_DOCK_ADC3_LEFT1	0x0118	/* Audio Dock ADC3 Left, 1st or 48kHz only */
1439 #define EMU_SRC_DOCK_ADC3_LEFT2	0x0119	/* Audio Dock ADC3 Left, 2nd or 96kHz */
1440 #define EMU_SRC_DOCK_ADC3_LEFT3	0x011a	/* Audio Dock ADC3 Left, 3rd or 192kHz */
1441 #define EMU_SRC_DOCK_ADC3_LEFT4	0x011b	/* Audio Dock ADC3 Left, 4th or 192kHz */
1442 #define EMU_SRC_DOCK_ADC3_RIGHT1	0x011c	/* Audio Dock ADC3 Right, 1st or 48kHz only */
1443 #define EMU_SRC_DOCK_ADC3_RIGHT2	0x011d	/* Audio Dock ADC3 Right, 2nd or 96kHz */
1444 #define EMU_SRC_DOCK_ADC3_RIGHT3	0x011e	/* Audio Dock ADC3 Right, 3rd or 192kHz */
1445 #define EMU_SRC_DOCK_ADC3_RIGHT4	0x011f	/* Audio Dock ADC3 Right, 4th or 192kHz */
1446 #define EMU_SRC_HAMOA_ADC_LEFT1	0x0200	/* Hamoa ADC Left, 1st or 48kHz only */
1447 #define EMU_SRC_HAMOA_ADC_LEFT2	0x0202	/* Hamoa ADC Left, 2nd or 96kHz */
1448 #define EMU_SRC_HAMOA_ADC_LEFT3	0x0204	/* Hamoa ADC Left, 3rd or 192kHz */
1449 #define EMU_SRC_HAMOA_ADC_LEFT4	0x0206	/* Hamoa ADC Left, 4th or 192kHz */
1450 #define EMU_SRC_HAMOA_ADC_RIGHT1	0x0201	/* Hamoa ADC Right, 1st or 48kHz only */
1451 #define EMU_SRC_HAMOA_ADC_RIGHT2	0x0203	/* Hamoa ADC Right, 2nd or 96kHz */
1452 #define EMU_SRC_HAMOA_ADC_RIGHT3	0x0205	/* Hamoa ADC Right, 3rd or 192kHz */
1453 #define EMU_SRC_HAMOA_ADC_RIGHT4	0x0207	/* Hamoa ADC Right, 4th or 192kHz */
1457 #define EMU_SRC_HANA_SPDIF_LEFT1	0x0500	/* Hana SPDIF Left, 1st or 48kHz only */
1458 #define EMU_SRC_HANA_SPDIF_LEFT2	0x0502	/* Hana SPDIF Left, 2nd or 96kHz */
1459 #define EMU_SRC_HANA_SPDIF_RIGHT1	0x0501	/* Hana SPDIF Right, 1st or 48kHz only */
1460 #define EMU_SRC_HANA_SPDIF_RIGHT2	0x0503	/* Hana SPDIF Right, 2nd or 96kHz */
1463 /* Microdock S/PDIF Left, 1st or 48kHz only */
1465 /* Microdock S/PDIF Left, 2nd or 96kHz */
1467 /* Microdock S/PDIF Right, 1st or 48kHz only */
1469 /* Microdock S/PDIF Right, 2nd or 96kHz */
1564 	unsigned short gpr[32];		/* GPR number(s) */
1565 	unsigned int value[32];
1594 	unsigned char etram[32];	/* external TRAM address & data */
1748 	struct snd_emu10k1_pcm_mixer pcm_mixer[32];