Lines Matching +full:1 +full:khz
65 /* Clear pending interrupts by writing a 1 to */
155 /* NOTE: Each channel takes 1/64th of a sample */
172 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
173 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
174 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
178 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
179 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
192 #define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */
216 /* 1 = Force all 3 async digital inputs to use */
219 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
220 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
221 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
226 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
228 #define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
231 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
238 /* Should be set to 1 when the EMU10K1 is */
264 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
285 /* 0 == 1024 periods, [1..4] are not useful */
308 #define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop …
309 #define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop …
322 * bit 1: Lock P16V record memory cache.
327 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
335 /* PCI function 1 registers, address = <val> + PCIBASE1 */
360 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
361 #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
384 #define Z1 0x05 /* Filter delay memory 1 register */
407 /* 1 == full band, 7 == lowpass */
413 #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
420 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
427 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
428 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
429 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
437 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
470 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
473 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
475 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in…
479 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
493 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
496 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
499 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
553 #define CD1 0x21 /* Cache data 1 register */
587 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
588 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
589 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
590 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
591 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
592 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
593 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
594 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
595 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
596 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
597 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
603 /* is 16bit, 48KHz only. All 32 channels can be enabled */
606 #define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */
607 #define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */
608 #define FXWC_DEFAULTROUTE_A (1<<12)
609 #define FXWC_DEFAULTROUTE_D (1<<13)
610 #define FXWC_ADCLEFT (1<<18)
611 #define FXWC_CDROMSPDIFLEFT (1<<18)
612 #define FXWC_ADCRIGHT (1<<19)
613 #define FXWC_CDROMSPDIFRIGHT (1<<19)
614 #define FXWC_MIC (1<<20)
615 #define FXWC_ZOOMLEFT (1<<20)
616 #define FXWC_ZOOMRIGHT (1<<21)
617 #define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
618 #define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
720 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
729 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
730 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
731 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
745 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
746 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
765 #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
766 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
767 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
849 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
960 #define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */
980 #define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */
984 #define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */
1013 #define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */
1018 #define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */
1024 #define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */
1025 #define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */
1026 #define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */
1027 #define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */
1040 #define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */
1043 #define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */
1046 #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */
1050 #define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */
1051 #define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */
1052 #define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */
1053 #define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */
1056 #define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */
1057 #define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */
1058 #define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */
1059 #define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */
1060 #define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */
1063 #define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */
1067 #define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */
1094 #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
1113 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1116 * 0x01, 0x00: Dock DAC 1 Left
1117 * 0x01, 0x04: Dock DAC 1 Right
1144 * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1147 * 0x01, 0x00: Dock DAC 1 Left
1148 * 0x01, 0x04: Dock DAC 1 Right
1165 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1175 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1185 * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1188 * 0x01, 0x00: Dock DAC 1 Left
1189 * 0x01, 0x04: Dock DAC 1 Right
1231 #define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1232 #define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1233 #define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1234 #define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */
1235 #define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1236 #define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1237 #define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1238 #define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */
1239 #define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1240 #define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1241 #define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1242 #define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */
1243 #define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1244 #define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1245 #define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1246 #define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */
1247 #define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1248 #define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1249 #define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1250 #define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */
1251 #define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */
1252 #define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */
1253 #define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1254 #define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1255 #define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1256 #define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */
1257 #define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */
1258 #define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */
1259 #define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1260 #define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1261 #define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1262 #define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */
1263 #define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */
1264 #define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */
1265 #define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1266 #define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1267 #define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1268 #define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */
1269 #define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */
1270 #define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */
1271 #define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */
1272 #define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */
1273 #define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */
1274 #define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */
1275 #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */
1276 #define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */
1277 #define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */
1278 #define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */
1279 #define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */
1280 #define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */
1281 #define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */
1282 #define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */
1292 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */
1294 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */
1296 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */
1298 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */
1303 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1305 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1312 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1317 * 0x01, 0x08: Dock ADC 1 Left
1318 * 0x01, 0x0c: Dock ADC 1 Right
1336 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1341 * 0x01, 0x08: Dock ADC 1 Left
1342 * 0x01, 0x0c: Dock ADC 1 Right
1360 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1373 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1386 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1391 * 0x01, 0x08: Dock ADC 1 Left
1392 * 0x01, 0x0c: Dock ADC 1 Right
1414 #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */
1415 #define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */
1416 #define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */
1417 #define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */
1418 #define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */
1419 #define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */
1420 #define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */
1421 #define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */
1422 #define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */
1423 #define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */
1424 #define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */
1425 #define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */
1426 #define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */
1427 #define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */
1428 #define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */
1429 #define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */
1430 #define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */
1431 #define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */
1432 #define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */
1433 #define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */
1434 #define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */
1435 #define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */
1436 #define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */
1437 #define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */
1438 #define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */
1439 #define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */
1440 #define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */
1441 #define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */
1442 #define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */
1443 #define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */
1444 #define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */
1445 #define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */
1446 #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */
1447 #define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */
1448 #define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */
1449 #define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */
1450 #define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */
1451 #define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */
1452 #define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */
1453 #define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */
1457 #define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */
1458 #define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */
1459 #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */
1460 #define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */
1463 /* Microdock S/PDIF Left, 1st or 48kHz only */
1465 /* Microdock S/PDIF Left, 2nd or 96kHz */
1467 /* Microdock S/PDIF Right, 1st or 48kHz only */
1469 /* Microdock S/PDIF Right, 2nd or 96kHz */
1490 unsigned int use: 1,
1491 pcm: 1,
1492 efx: 1,
1493 synth: 1,
1494 midi: 1;
1539 ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
1542 ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsign…
1556 …0k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
1563 unsigned int count; /* count of GPR (1..16) */
1582 unsigned int valid: 1,
1583 opened: 1,
1584 active: 1;
1648 unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */
1649 unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
1656 unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */
1674 unsigned int optical_in; /* 0:SPDIF, 1:ADAT */
1675 unsigned int optical_out; /* 0:SPDIF, 1:ADAT */
1684 unsigned int tos_link: 1, /* tos link detected */
1685 rear_ac97: 1, /* rear channels are on AC'97 */
1686 enable_ir: 1;
1687 unsigned int support_tlv :1;