Lines Matching +full:serial +full:- +full:output
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define CS8427_REG_AUTOINC 0x80 /* flag - autoincrement */
34 #define CS8427_REG_QSUBCODE 0x14 /* 0x14-0x1d (10 bytes) */
40 #define CS8427_SWCLK (1<<7) /* 0 = RMCK default, 1 = OMCK output on RMCK pin */
42 #define CS8427_MUTESAO (1<<5) /* mute control for the serial audio output port, 0 = disabled, 1 = …
43 #define CS8427_MUTEAES (1<<4) /* mute control for the AES transmitter output, 0 = disabled, 1 = en…
44 #define CS8427_INTMASK (3<<1) /* interrupt output pin setup mask */
48 #define CS8427_TCBLDIR (1<<0) /* 0 = TCBL is an input, 1 = TCBL is an output */
62 #define CS8427_TXOFF (1<<6) /* AES3 transmitter Output, 0 = normal operation, 1 = off (0V) */
63 #define CS8427_AESBP (1<<5) /* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */
65 #define CS8427_TXDSERIAL (1<<3) /* TXD - serial audio input port */
66 #define CS8427_TXAES3DRECEIVER (2<<3) /* TXD - AES3 receiver */
67 #define CS8427_SPDMASK (3<<1) /* Serial Audio Output Port Data Source Mask */
68 #define CS8427_SPDSERIAL (1<<1) /* SPD - serial audio input port */
69 #define CS8427_SPDAES3RECEIVER (2<<1) /* SPD - AES3 receiver */
77 #define CS8427_OUTC (1<<3) /* Output Time Base, 0 = OMCK, 1 = recovered input clock */
89 #define CS8427_SIRES24 (0<<4) /* SIRES 24-bit */
90 #define CS8427_SIRES20 (1<<4) /* SIRES 20-bit */
91 #define CS8427_SIRES16 (2<<4) /* SIRES 16-bit */
92 … (1<<3) /* Justification of SDIN data relative to ILRCK, 0 = left-justified, 1 = right-justified */
93 #define CS8427_SIDEL (1<<2) /* Delay of SDIN data relative to ILRCK for left-justified data format…
100 #define CS8427_SORESMASK (3<<4) /* Resolution of the output data on SDOUT and AES3 output */
101 #define CS8427_SORES24 (0<<4) /* SIRES 24-bit */
102 #define CS8427_SORES20 (1<<4) /* SIRES 20-bit */
103 #define CS8427_SORES16 (2<<4) /* SIRES 16-bit */
105 …(1<<3) /* Justification of SDOUT data relative to OLRCK, 0 = left-justified, 1 = right-justified */
106 #define CS8427_SODEL (1<<2) /* Delay of SDOUT data relative to OLRCK for left-justified data forma…
112 #define CS8427_OSLIP (1<<6) /* Serial audio output port data slip interrupt */
113 #define CS8427_DETC (1<<2) /* D to E C-buffer transfer interrupt */
114 #define CS8427_EFTC (1<<1) /* E to F C-buffer transfer interrupt */
118 #define CS8427_DETU (1<<3) /* D to E U-buffer transfer interrupt */
119 #define CS8427_EFTU (1<<2) /* E to F U-buffer transfer interrupt */
120 #define CS8427_QCH (1<<1) /* A new block of Q-subcode data is available for reading */
143 #define CS8427_QCRC (1<<6) /* Q-subcode data CRC error indicator */
148 #define CS8427_BIP (1<<1) /* Bi-phase error bit */
160 #define CS8427_UD (1<<4) /* User data pin (U) direction, 0 = input, 1 = output */
164 #define CS8427_DETUI (1<<1) /* D to E U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
165 #define CS8427_EFTUI (1<<1) /* E to F U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */