Lines Matching +full:0 +full:x72
25 #define AC97_SIGMATEL_OUTSEL 0x64 /* Output Select, STAC9758 */
26 #define AC97_SIGMATEL_INSEL 0x66 /* Input Select, STAC9758 */
27 #define AC97_SIGMATEL_IOMISC 0x68 /* STAC9758 */
28 #define AC97_SIGMATEL_ANALOG 0x6c /* Analog Special */
29 #define AC97_SIGMATEL_DAC2INVERT 0x6e
30 #define AC97_SIGMATEL_BIAS1 0x70
31 #define AC97_SIGMATEL_BIAS2 0x72
32 #define AC97_SIGMATEL_VARIOUS 0x72 /* STAC9758 */
33 #define AC97_SIGMATEL_MULTICHN 0x74 /* Multi-Channel programming */
34 #define AC97_SIGMATEL_CIC1 0x76
35 #define AC97_SIGMATEL_CIC2 0x78
38 #define AC97_AD_TEST 0x5a /* test register */
39 #define AC97_AD_TEST2 0x5c /* undocumented test register 2 */
41 #define AC97_AD_CODEC_CFG 0x70 /* codec configuration */
42 #define AC97_AD_JACK_SPDIF 0x72 /* Jack Sense & S/PDIF */
43 #define AC97_AD_SERIAL_CFG 0x74 /* Serial Configuration */
44 #define AC97_AD_MISC 0x76 /* Misc Control Bits */
48 #define AC97_CSR_ACMODE 0x5e /* AC Mode Register */
49 #define AC97_CSR_MISC_CRYSTAL 0x60 /* Misc Crystal Control */
50 #define AC97_CSR_SPDIF 0x68 /* S/PDIF Register */
51 #define AC97_CSR_SERIAL 0x6a /* Serial Port Control */
52 #define AC97_CSR_SPECF_ADDR 0x6c /* Special Feature Address */
53 #define AC97_CSR_SPECF_DATA 0x6e /* Special Feature Data */
54 #define AC97_CSR_BDI_STATUS 0x7a /* BDI Status */
57 #define AC97_CXR_AUDIO_MISC 0x5c
60 #define AC97_CXR_SPDIF_MASK (3<<0)
61 #define AC97_CXR_SPDIF_PCM 0x0
62 #define AC97_CXR_SPDIF_AC3 0x2
65 #define AC97_ALC650_SPDIF_INPUT_STATUS1 0x60
67 #define AC97_ALC650_PRO 0x0001 /* Professional status */
68 #define AC97_ALC650_NAUDIO 0x0002 /* Non audio stream */
69 #define AC97_ALC650_COPY 0x0004 /* Copyright status */
70 #define AC97_ALC650_PRE 0x0038 /* Preemphasis status */
72 #define AC97_ALC650_MODE 0x00C0 /* Preemphasis status */
74 #define AC97_ALC650_CC_MASK 0x7f00 /* Category Code mask */
76 #define AC97_ALC650_L 0x8000 /* Generation Level status */
78 #define AC97_ALC650_SPDIF_INPUT_STATUS2 0x62
80 #define AC97_ALC650_SOUCE_MASK 0x000f /* Source number */
81 #define AC97_ALC650_CHANNEL_MASK 0x00f0 /* Channel number */
83 #define AC97_ALC650_SPSR_MASK 0x0f00 /* S/PDIF Sample Rate bits */
85 #define AC97_ALC650_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */
86 #define AC97_ALC650_SPSR_48K 0x0200 /* Use 48kHz Sample rate */
87 #define AC97_ALC650_SPSR_32K 0x0300 /* Use 32kHz Sample rate */
88 #define AC97_ALC650_CLOCK_ACCURACY 0x3000 /* Clock accuracy */
90 #define AC97_ALC650_CLOCK_LOCK 0x4000 /* Clock locked status */
91 #define AC97_ALC650_V 0x8000 /* Validity status */
93 #define AC97_ALC650_SURR_DAC_VOL 0x64
94 #define AC97_ALC650_LFE_DAC_VOL 0x66
95 #define AC97_ALC650_UNKNOWN1 0x68
96 #define AC97_ALC650_MULTICH 0x6a
97 #define AC97_ALC650_UNKNOWN2 0x6c
98 #define AC97_ALC650_REVISION 0x6e
99 #define AC97_ALC650_UNKNOWN3 0x70
100 #define AC97_ALC650_UNKNOWN4 0x72
101 #define AC97_ALC650_MISC 0x74
102 #define AC97_ALC650_GPIO_SETUP 0x76
103 #define AC97_ALC650_GPIO_STATUS 0x78
104 #define AC97_ALC650_CLOCK 0x7a
107 #define AC97_YMF7X3_DIT_CTRL 0x66 /* DIT Control (YMF743) / 2 (YMF753) */
108 #define AC97_YMF7X3_3D_MODE_SEL 0x68 /* 3D Mode Select */
111 #define AC97_CM9738_VENDOR_CTRL 0x5a
112 #define AC97_CM9739_MULTI_CHAN 0x64
113 #define AC97_CM9739_SPDIF_IN_STATUS 0x68 /* 32bit */
114 #define AC97_CM9739_SPDIF_CTRL 0x6c
117 #define AC97_WM97XX_FMIXER_VOL 0x72
118 #define AC97_WM9704_RMIXER_VOL 0x74
119 #define AC97_WM9704_TEST 0x5a
120 #define AC97_WM9704_RPCM_VOL 0x70
121 #define AC97_WM9711_OUT3VOL 0x16
125 #define AC97_SCAP_AUDIO (1<<0) /* audio codec 97 */
139 #define AC97_HAS_PC_BEEP (1<<0) /* force PC Speaker usage */
161 #define AC97_RATES_FRONT_DAC 0
228 unsigned short num; /* number of codec: 0 = primary, 1 = secondary */
229 unsigned short addr; /* physical address of codec [0-3] */
248 unsigned short num; /* number of codec: 0 = primary, 1 = secondary */
249 unsigned short addr; /* physical address of codec [0-3] */
251 unsigned short caps; /* capabilities (register 0) */
259 unsigned short regs[0x80]; /* register cache */
260 DECLARE_BITMAP(reg_accessed, 0x80); /* bit flags */
263 unsigned short unchained[3]; // 0 = C34, 1 = C79, 2 = C69
264 unsigned short chained[3]; // 0 = C34, 1 = C79, 2 = C69
304 return (ac97->ext_id & AC97_EI_AMAP) != 0; in ac97_can_amap()
308 return (ac97->ext_id & AC97_EI_SPDIF) != 0; in ac97_can_spdif()
332 return 0; in snd_ac97_update_power()
345 AC97_TUNE_NONE = 0, /* nothing extra to do */
359 unsigned short mask; /* device id bit mask, 0 = accept all */
360 unsigned int codec_id; /* codec id (if any), 0 = accept all */
397 } r[2]; /* 0 = standard rates, 1 = double rates */