Lines Matching +full:4 +full:x
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
17 #define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0)) argument
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
27 #define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15)) argument
29 #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15) argument
30 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8)) argument
32 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8) argument
33 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1)) argument
35 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1) argument
38 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4)) argument
39 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4)
40 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x) (((x) & GENMASK(11, 4)) >> 4) argument
41 #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x) ((x) & GENMASK(3, 0)) argument
44 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
48 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
51 #define DEV_MAC_TAGS_CFG_TAG_ID(x) (((x) << 16) & GENMASK(31, 16)) argument
53 #define DEV_MAC_TAGS_CFG_TAG_ID_X(x) (((x) & GENMASK(31, 16)) >> 16) argument
62 #define DEV_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8)) argument
64 #define DEV_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8) argument
65 #define DEV_MAC_IFG_CFG_RX_IFG2(x) (((x) << 4) & GENMASK(7, 4)) argument
66 #define DEV_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4)
67 #define DEV_MAC_IFG_CFG_RX_IFG2_X(x) (((x) & GENMASK(7, 4)) >> 4) argument
68 #define DEV_MAC_IFG_CFG_RX_IFG1(x) ((x) & GENMASK(3, 0)) argument
74 #define DEV_MAC_HDX_CFG_SEED(x) (((x) << 16) & GENMASK(23, 16)) argument
76 #define DEV_MAC_HDX_CFG_SEED_X(x) (((x) & GENMASK(23, 16)) >> 16) argument
79 #define DEV_MAC_HDX_CFG_LATE_COL_POS(x) ((x) & GENMASK(6, 0)) argument
82 #define DEV_MAC_DBG_CFG_TBI_MODE BIT(4)
90 #define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY BIT(4)
96 #define PCS1G_CFG_LINK_STATUS_TYPE BIT(4)
100 #define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
104 #define PCS1G_SD_CFG_SD_POL BIT(4)
107 #define PCS1G_ANEG_CFG_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16)) argument
109 #define PCS1G_ANEG_CFG_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16) argument
114 #define PCS1G_ANEG_NP_CFG_NP_TX(x) (((x) << 16) & GENMASK(31, 16)) argument
116 #define PCS1G_ANEG_NP_CFG_NP_TX_X(x) (((x) & GENMASK(31, 16)) >> 16) argument
119 #define PCS1G_LB_CFG_RA_ENA BIT(4)
127 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16)) argument
129 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16) argument
130 #define PCS1G_ANEG_STATUS_PR BIT(4)
134 #define PCS1G_LINK_STATUS_DELAY_VAR(x) (((x) << 12) & GENMASK(15, 12)) argument
136 #define PCS1G_LINK_STATUS_DELAY_VAR_X(x) (((x) & GENMASK(15, 12)) >> 12) argument
138 #define PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
141 #define PCS1G_STICKY_LINK_DOWN_STICKY BIT(4)
147 #define PCS1G_LPI_CFG_LPI_RX_WTIM(x) (((x) << 4) & GENMASK(5, 4)) argument
148 #define PCS1G_LPI_CFG_LPI_RX_WTIM_M GENMASK(5, 4)
149 #define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x) (((x) & GENMASK(5, 4)) >> 4) argument
156 #define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY BIT(4)
160 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x) (((x) << 8) & GENMASK(15, 8)) argument
162 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8) argument
163 #define PCS1G_TSTPAT_STATUS_JTP_ERR BIT(4)
171 #define DEV_PCS_FX100_CFG_RXBITSEL(x) (((x) << 12) & GENMASK(15, 12)) argument
173 #define DEV_PCS_FX100_CFG_RXBITSEL_X(x) (((x) & GENMASK(15, 12)) >> 12) argument
174 #define DEV_PCS_FX100_CFG_SIGDET_CFG(x) (((x) << 9) & GENMASK(10, 9)) argument
176 #define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x) (((x) & GENMASK(10, 9)) >> 9) argument
178 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x) (((x) << 4) & GENMASK(7, 4)) argument
179 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M GENMASK(7, 4)
180 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x) (((x) & GENMASK(7, 4)) >> 4) argument
186 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x) (((x) << 8) & GENMASK(11, 8)) argument
188 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x) (((x) & GENMASK(11, 8)) >> 8) argument
192 #define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4)