Lines Matching +full:0 +full:x02c00000
32 QE_CLK_NONE = 0,
131 return 0; in cpm_muram_dma()
226 return 0; in qe_alive_during_sleep()
270 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
283 __be32 traps[16]; /* Trap addresses, 0 == ignore */
327 #define BD_STATUS_MASK 0xffff0000
328 #define BD_LENGTH_MASK 0x0000ffff
336 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
337 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
338 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
339 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
350 = 0x3f, /* LookupKey parsed by the Generate LookupKey
353 = 0x5f, /* LookupKey parsed by the Generate LookupKey
360 = 0x0,/* not used */
386 COMM_DIR_NONE = 0,
396 #define QE_CMXUCR_MII_ENET_MNG 0x00007000
398 #define QE_CMXUCR_GRANT 0x00008000
399 #define QE_CMXUCR_TSA 0x00004000
400 #define QE_CMXUCR_BKPT 0x00000100
401 #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
405 #define QE_CMXGCR_MII_ENET_MNG 0x00007000
407 #define QE_CMXGCR_USBCS 0x0000000f
408 #define QE_CMXGCR_USBCS_CLK3 0x1
409 #define QE_CMXGCR_USBCS_CLK5 0x2
410 #define QE_CMXGCR_USBCS_CLK7 0x3
411 #define QE_CMXGCR_USBCS_CLK9 0x4
412 #define QE_CMXGCR_USBCS_CLK13 0x5
413 #define QE_CMXGCR_USBCS_CLK17 0x6
414 #define QE_CMXGCR_USBCS_CLK19 0x7
415 #define QE_CMXGCR_USBCS_CLK21 0x8
416 #define QE_CMXGCR_USBCS_BRG9 0x9
417 #define QE_CMXGCR_USBCS_BRG10 0xa
421 #define QE_CR_FLG 0x00010000
422 #define QE_RESET 0x80000000
423 #define QE_INIT_TX_RX 0x00000000
424 #define QE_INIT_RX 0x00000001
425 #define QE_INIT_TX 0x00000002
426 #define QE_ENTER_HUNT_MODE 0x00000003
427 #define QE_STOP_TX 0x00000004
428 #define QE_GRACEFUL_STOP_TX 0x00000005
429 #define QE_RESTART_TX 0x00000006
430 #define QE_CLOSE_RX_BD 0x00000007
431 #define QE_SWITCH_COMMAND 0x00000007
432 #define QE_SET_GROUP_ADDRESS 0x00000008
433 #define QE_START_IDMA 0x00000009
434 #define QE_MCC_STOP_RX 0x00000009
435 #define QE_ATM_TRANSMIT 0x0000000a
436 #define QE_HPAC_CLEAR_ALL 0x0000000b
437 #define QE_GRACEFUL_STOP_RX 0x0000001a
438 #define QE_RESTART_RX 0x0000001b
439 #define QE_HPAC_SET_PRIORITY 0x0000010b
440 #define QE_HPAC_STOP_TX 0x0000020b
441 #define QE_HPAC_STOP_RX 0x0000030b
442 #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
443 #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
444 #define QE_HPAC_START_TX 0x0000060b
445 #define QE_HPAC_START_RX 0x0000070b
446 #define QE_USB_STOP_TX 0x0000000a
447 #define QE_USB_RESTART_TX 0x0000000c
448 #define QE_QMC_STOP_TX 0x0000000c
449 #define QE_QMC_STOP_RX 0x0000000d
450 #define QE_SS7_SU_FIL_RESET 0x0000000e
452 #define QE_RESET_BCS 0x0000000a
453 #define QE_MCC_INIT_TX_RX_16 0x00000003
454 #define QE_MCC_STOP_TX 0x00000004
455 #define QE_MCC_INIT_TX_1 0x00000005
456 #define QE_MCC_INIT_RX_1 0x00000006
457 #define QE_MCC_RESET 0x00000007
458 #define QE_SET_TIMER 0x00000008
459 #define QE_RANDOM_NUMBER 0x0000000c
460 #define QE_ATM_MULTI_THREAD_INIT 0x00000011
461 #define QE_ASSIGN_PAGE 0x00000012
462 #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
463 #define QE_START_FLOW_CONTROL 0x00000014
464 #define QE_STOP_FLOW_CONTROL 0x00000015
465 #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
467 #define QE_ASSIGN_RISC 0x00000010
475 #define QE_CR_SUBBLOCK_INVALID 0x00000000
476 #define QE_CR_SUBBLOCK_USB 0x03200000
477 #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
478 #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
479 #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
480 #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
481 #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
482 #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
483 #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
484 #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
485 #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
486 #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
487 #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
488 #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
489 #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
490 #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
491 #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
492 #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
493 #define QE_CR_SUBBLOCK_MCC1 0x03800000
494 #define QE_CR_SUBBLOCK_MCC2 0x03a00000
495 #define QE_CR_SUBBLOCK_MCC3 0x03000000
496 #define QE_CR_SUBBLOCK_IDMA1 0x02800000
497 #define QE_CR_SUBBLOCK_IDMA2 0x02a00000
498 #define QE_CR_SUBBLOCK_IDMA3 0x02c00000
499 #define QE_CR_SUBBLOCK_IDMA4 0x02e00000
500 #define QE_CR_SUBBLOCK_HPAC 0x01e00000
501 #define QE_CR_SUBBLOCK_SPI1 0x01400000
502 #define QE_CR_SUBBLOCK_SPI2 0x01600000
503 #define QE_CR_SUBBLOCK_RAND 0x01c00000
504 #define QE_CR_SUBBLOCK_TIMER 0x01e00000
505 #define QE_CR_SUBBLOCK_GENERAL 0x03c00000
508 #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
509 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
510 #define QE_CR_PROTOCOL_QMC 0x02
511 #define QE_CR_PROTOCOL_UART 0x04
512 #define QE_CR_PROTOCOL_ATM_POS 0x0A
513 #define QE_CR_PROTOCOL_ETHERNET 0x0C
514 #define QE_CR_PROTOCOL_L2_SWITCH 0x0D
517 #define QE_BRGC_ENABLE 0x00010000
519 #define QE_BRGC_DIVISOR_MAX 0xFFF
523 #define QE_GTCFR1_PCAS 0x80
524 #define QE_GTCFR1_STP2 0x20
525 #define QE_GTCFR1_RST2 0x10
526 #define QE_GTCFR1_GM2 0x08
527 #define QE_GTCFR1_GM1 0x04
528 #define QE_GTCFR1_STP1 0x02
529 #define QE_GTCFR1_RST1 0x01
532 #define QE_SDSR_BER1 0x02000000
533 #define QE_SDSR_BER2 0x01000000
535 #define QE_SDMR_GLB_1_MSK 0x80000000
536 #define QE_SDMR_ADR_SEL 0x20000000
537 #define QE_SDMR_BER1_MSK 0x02000000
538 #define QE_SDMR_BER2_MSK 0x01000000
539 #define QE_SDMR_EB1_MSK 0x00800000
540 #define QE_SDMR_ER1_MSK 0x00080000
541 #define QE_SDMR_ER2_MSK 0x00040000
542 #define QE_SDMR_CEN_MASK 0x0000E000
543 #define QE_SDMR_SBER_1 0x00000200
544 #define QE_SDMR_SBER_2 0x00000200
545 #define QE_SDMR_EB1_PR_MASK 0x000000C0
546 #define QE_SDMR_ER1_PR 0x00000008
553 #define QE_SDEBCR_BA_MASK 0x01FFFFFF
556 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
557 #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
558 #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
561 #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
562 #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
563 #define QE_IRAM_READY 0x80000000 /* Ready */
566 #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
567 #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
568 #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
569 #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
570 #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
573 #define UCC_GUEMR_MODE_MASK_RX 0x02
574 #define UCC_GUEMR_MODE_FAST_RX 0x02
575 #define UCC_GUEMR_MODE_SLOW_RX 0x00
576 #define UCC_GUEMR_MODE_MASK_TX 0x01
577 #define UCC_GUEMR_MODE_FAST_TX 0x01
578 #define UCC_GUEMR_MODE_SLOW_TX 0x00
580 #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
605 #define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
606 #define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
607 #define UCC_SLOW_GUMR_H_REVD 0x00002000
608 #define UCC_SLOW_GUMR_H_TRX 0x00001000
609 #define UCC_SLOW_GUMR_H_TTX 0x00000800
610 #define UCC_SLOW_GUMR_H_CDP 0x00000400
611 #define UCC_SLOW_GUMR_H_CTSP 0x00000200
612 #define UCC_SLOW_GUMR_H_CDS 0x00000100
613 #define UCC_SLOW_GUMR_H_CTSS 0x00000080
614 #define UCC_SLOW_GUMR_H_TFL 0x00000040
615 #define UCC_SLOW_GUMR_H_RFW 0x00000020
616 #define UCC_SLOW_GUMR_H_TXSY 0x00000010
617 #define UCC_SLOW_GUMR_H_4SYNC 0x00000004
618 #define UCC_SLOW_GUMR_H_8SYNC 0x00000008
619 #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
620 #define UCC_SLOW_GUMR_H_RTSM 0x00000002
621 #define UCC_SLOW_GUMR_H_RSYN 0x00000001
623 #define UCC_SLOW_GUMR_L_TCI 0x10000000
624 #define UCC_SLOW_GUMR_L_RINV 0x02000000
625 #define UCC_SLOW_GUMR_L_TINV 0x01000000
626 #define UCC_SLOW_GUMR_L_TEND 0x00040000
627 #define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
628 #define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
629 #define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
630 #define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
631 #define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
632 #define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
633 #define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
634 #define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
635 #define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
636 #define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
637 #define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
638 #define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
639 #define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
640 #define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
641 #define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
642 #define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
643 #define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
644 #define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
645 #define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
646 #define UCC_SLOW_GUMR_L_ENR 0x00000020
647 #define UCC_SLOW_GUMR_L_ENT 0x00000010
648 #define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
649 #define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
650 #define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
651 #define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
652 #define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
655 #define UCC_FAST_GUMR_LOOPBACK 0x40000000
656 #define UCC_FAST_GUMR_TCI 0x20000000
657 #define UCC_FAST_GUMR_TRX 0x10000000
658 #define UCC_FAST_GUMR_TTX 0x08000000
659 #define UCC_FAST_GUMR_CDP 0x04000000
660 #define UCC_FAST_GUMR_CTSP 0x02000000
661 #define UCC_FAST_GUMR_CDS 0x01000000
662 #define UCC_FAST_GUMR_CTSS 0x00800000
663 #define UCC_FAST_GUMR_TXSY 0x00020000
664 #define UCC_FAST_GUMR_RSYN 0x00010000
665 #define UCC_FAST_GUMR_SYNL_MASK 0x0000C000
666 #define UCC_FAST_GUMR_SYNL_16 0x0000C000
667 #define UCC_FAST_GUMR_SYNL_8 0x00008000
668 #define UCC_FAST_GUMR_SYNL_AUTO 0x00004000
669 #define UCC_FAST_GUMR_RTSM 0x00002000
670 #define UCC_FAST_GUMR_REVD 0x00000400
671 #define UCC_FAST_GUMR_ENR 0x00000020
672 #define UCC_FAST_GUMR_ENT 0x00000010
675 #define UCC_UART_UCCE_AB 0x0200
676 #define UCC_UART_UCCE_IDLE 0x0100
677 #define UCC_UART_UCCE_GRA 0x0080
678 #define UCC_UART_UCCE_BRKE 0x0040
679 #define UCC_UART_UCCE_BRKS 0x0020
680 #define UCC_UART_UCCE_CCR 0x0008
681 #define UCC_UART_UCCE_BSY 0x0004
682 #define UCC_UART_UCCE_TX 0x0002
683 #define UCC_UART_UCCE_RX 0x0001
686 #define UCC_HDLC_UCCE_GLR 0x1000
687 #define UCC_HDLC_UCCE_GLT 0x0800
688 #define UCC_HDLC_UCCE_IDLE 0x0100
689 #define UCC_HDLC_UCCE_BRKE 0x0040
690 #define UCC_HDLC_UCCE_BRKS 0x0020
691 #define UCC_HDLC_UCCE_TXE 0x0010
692 #define UCC_HDLC_UCCE_RXF 0x0008
693 #define UCC_HDLC_UCCE_BSY 0x0004
694 #define UCC_HDLC_UCCE_TXB 0x0002
695 #define UCC_HDLC_UCCE_RXB 0x0001
698 #define UCC_BISYNC_UCCE_GRA 0x0080
699 #define UCC_BISYNC_UCCE_TXE 0x0010
700 #define UCC_BISYNC_UCCE_RCH 0x0008
701 #define UCC_BISYNC_UCCE_BSY 0x0004
702 #define UCC_BISYNC_UCCE_TXB 0x0002
703 #define UCC_BISYNC_UCCE_RXB 0x0001
706 #define UCC_GETH_UCCE_MPD 0x80000000
707 #define UCC_GETH_UCCE_SCAR 0x40000000
708 #define UCC_GETH_UCCE_GRA 0x20000000
709 #define UCC_GETH_UCCE_CBPR 0x10000000
710 #define UCC_GETH_UCCE_BSY 0x08000000
711 #define UCC_GETH_UCCE_RXC 0x04000000
712 #define UCC_GETH_UCCE_TXC 0x02000000
713 #define UCC_GETH_UCCE_TXE 0x01000000
714 #define UCC_GETH_UCCE_TXB7 0x00800000
715 #define UCC_GETH_UCCE_TXB6 0x00400000
716 #define UCC_GETH_UCCE_TXB5 0x00200000
717 #define UCC_GETH_UCCE_TXB4 0x00100000
718 #define UCC_GETH_UCCE_TXB3 0x00080000
719 #define UCC_GETH_UCCE_TXB2 0x00040000
720 #define UCC_GETH_UCCE_TXB1 0x00020000
721 #define UCC_GETH_UCCE_TXB0 0x00010000
722 #define UCC_GETH_UCCE_RXB7 0x00008000
723 #define UCC_GETH_UCCE_RXB6 0x00004000
724 #define UCC_GETH_UCCE_RXB5 0x00002000
725 #define UCC_GETH_UCCE_RXB4 0x00001000
726 #define UCC_GETH_UCCE_RXB3 0x00000800
727 #define UCC_GETH_UCCE_RXB2 0x00000400
728 #define UCC_GETH_UCCE_RXB1 0x00000200
729 #define UCC_GETH_UCCE_RXB0 0x00000100
730 #define UCC_GETH_UCCE_RXF7 0x00000080
731 #define UCC_GETH_UCCE_RXF6 0x00000040
732 #define UCC_GETH_UCCE_RXF5 0x00000020
733 #define UCC_GETH_UCCE_RXF4 0x00000010
734 #define UCC_GETH_UCCE_RXF3 0x00000008
735 #define UCC_GETH_UCCE_RXF2 0x00000004
736 #define UCC_GETH_UCCE_RXF1 0x00000002
737 #define UCC_GETH_UCCE_RXF0 0x00000001
740 #define UCC_UART_UPSMR_FLC 0x8000
741 #define UCC_UART_UPSMR_SL 0x4000
742 #define UCC_UART_UPSMR_CL_MASK 0x3000
743 #define UCC_UART_UPSMR_CL_8 0x3000
744 #define UCC_UART_UPSMR_CL_7 0x2000
745 #define UCC_UART_UPSMR_CL_6 0x1000
746 #define UCC_UART_UPSMR_CL_5 0x0000
747 #define UCC_UART_UPSMR_UM_MASK 0x0c00
748 #define UCC_UART_UPSMR_UM_NORMAL 0x0000
749 #define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
750 #define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
751 #define UCC_UART_UPSMR_FRZ 0x0200
752 #define UCC_UART_UPSMR_RZS 0x0100
753 #define UCC_UART_UPSMR_SYN 0x0080
754 #define UCC_UART_UPSMR_DRT 0x0040
755 #define UCC_UART_UPSMR_PEN 0x0010
756 #define UCC_UART_UPSMR_RPM_MASK 0x000c
757 #define UCC_UART_UPSMR_RPM_ODD 0x0000
758 #define UCC_UART_UPSMR_RPM_LOW 0x0004
759 #define UCC_UART_UPSMR_RPM_EVEN 0x0008
760 #define UCC_UART_UPSMR_RPM_HIGH 0x000C
761 #define UCC_UART_UPSMR_TPM_MASK 0x0003
762 #define UCC_UART_UPSMR_TPM_ODD 0x0000
763 #define UCC_UART_UPSMR_TPM_LOW 0x0001
764 #define UCC_UART_UPSMR_TPM_EVEN 0x0002
765 #define UCC_UART_UPSMR_TPM_HIGH 0x0003
768 #define UCC_GETH_UPSMR_FTFE 0x80000000
769 #define UCC_GETH_UPSMR_PTPE 0x40000000
770 #define UCC_GETH_UPSMR_ECM 0x04000000
771 #define UCC_GETH_UPSMR_HSE 0x02000000
772 #define UCC_GETH_UPSMR_PRO 0x00400000
773 #define UCC_GETH_UPSMR_CAP 0x00200000
774 #define UCC_GETH_UPSMR_RSH 0x00100000
775 #define UCC_GETH_UPSMR_RPM 0x00080000
776 #define UCC_GETH_UPSMR_R10M 0x00040000
777 #define UCC_GETH_UPSMR_RLPB 0x00020000
778 #define UCC_GETH_UPSMR_TBIM 0x00010000
779 #define UCC_GETH_UPSMR_RES1 0x00002000
780 #define UCC_GETH_UPSMR_RMM 0x00001000
781 #define UCC_GETH_UPSMR_CAM 0x00000400
782 #define UCC_GETH_UPSMR_BRO 0x00000200
783 #define UCC_GETH_UPSMR_SMM 0x00000080
784 #define UCC_GETH_UPSMR_SGMM 0x00000020
787 #define UCC_HDLC_UPSMR_RTE 0x02000000
788 #define UCC_HDLC_UPSMR_BUS 0x00200000
789 #define UCC_HDLC_UPSMR_CW8 0x00007000
792 #define UCC_SLOW_TOD 0x8000
793 #define UCC_FAST_TOD 0x8000
797 #define UCC_BMR_GBL 0x20
798 #define UCC_BMR_BO_BE 0x10
799 #define UCC_BMR_CETM 0x04
800 #define UCC_BMR_DTB 0x02
801 #define UCC_BMR_BDB 0x01
804 #define FC_GBL 0x20
805 #define FC_DTB_LCL 0x02
806 #define UCC_FAST_FUNCTION_CODE_GBL 0x20
807 #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
808 #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01