Lines Matching +full:write +full:- +full:only
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
45 #define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
47 #define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
48 …ne AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
65 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
67 #define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
74 #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
97 #define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
109 #define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
114 #define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
115 #define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
116 #define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
117 #define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
119 #define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
120 #define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
121 #define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */