Lines Matching +full:1 +full:ghz
16 #define SSB_FLASH2 0x1c000000U /* Flash Region 2 (region 1 shadowed here) */
20 #define SSB_FLASH1 0x1fc00000U /* Flash Region 1 */
21 #define SSB_FLASH1_SZ 0x00400000U /* Size of Flash Region 1 */
23 #define SSB_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
44 #define SSB_BAR1_WIN 0x84 /* Backplane address space 1 */
47 #define SSB_BAR1_CONTROL 0x8c /* Address space 1 burst control */
64 #define SSB_IPSFLAG_IRQ1 0x0000003F /* which sbflags get routed to mips interrupt 1 */
98 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
185 /* SPROM Revision 1 */
196 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
197 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
209 #define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
211 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
236 /* SPROM Revision 2 (inherits from rev 1) */
264 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
281 #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
283 #define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
293 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
294 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
303 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
310 #define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
315 #define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
320 #define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
325 #define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
330 #define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
335 #define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
340 #define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
345 #define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
357 #define SSB_SPROM4_2G_MAXP_ITSSI 0x00 /* 2 GHz ITSSI and 2 GHz Max Power */
361 #define SSB_SPROM4_2G_PA_0 0x02 /* 2 GHz power amp */
365 #define SSB_SPROM4_5G_MAXP_ITSSI 0x0A /* 5 GHz ITSSI and 5.3 GHz Max Power */
369 #define SSB_SPROM4_5GHL_MAXP 0x0C /* 5.2 GHz and 5.8 GHz Max Power */
373 #define SSB_SPROM4_5G_PA_0 0x0E /* 5.3 GHz power amp */
377 #define SSB_SPROM4_5GL_PA_0 0x16 /* 5.2 GHz power amp */
381 #define SSB_SPROM4_5GH_PA_0 0x1E /* 5.8 GHz power amp */
387 #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
389 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
391 #define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
393 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
409 #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
411 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
426 #define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
428 #define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
447 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
461 #define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
469 #define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
477 #define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
478 #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
479 #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
481 #define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
482 #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
483 #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
486 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
488 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
495 #define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
546 #define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
549 #define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
553 #define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
557 #define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
560 #define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
563 #define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
568 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
569 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
570 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
572 #define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
575 #define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
576 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
577 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
579 #define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
580 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
581 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
583 #define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
586 #define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
589 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
594 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
595 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
596 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
597 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
668 #define SSB_ADM_TYPE1 1