Lines Matching +full:serial +full:- +full:clk +full:- +full:low
1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * gpio interface, extbus, and support for serial and parallel flashes.
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
34 #define SSB_CHIPCO_FLASHT_STSER 0x00000100 /* ST serial flash */
35 #define SSB_CHIPCO_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
58 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
169 #define SSB_CHIPCO_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
170 #define SSB_CHIPCO_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
267 #define SSB_PMU0_PLLCTL1_WILD_IMSK 0xF0000000 /* Wild int mask (low nibble) */
305 #define SSB_PMU1_PLLCTL5_CLKDRV 0xFFFFFF00 /* clk drv */
395 /** Chip specific Chip-Status register contents. */
410 /** Macros to determine SPROM presence based on Chip-Status register. */
444 #define SSB_CHIPCO_CLK_F6_3 0x03 /* 6-bit fields like */
450 #define SSB_CHIPCO_CLK_F5_BIAS 5 /* 5-bit fields get this added */
495 /** Flash-specific control/status values */
506 #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
509 #define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
556 #define SSB_CHIPCO_OTP_SWLIM_OFF (-8)
561 #define SSB_CHIPCO_OTP_BOUNDARY_OFF (-4)
562 #define SSB_CHIPCO_OTP_HWSIGN_OFF (-3)
563 #define SSB_CHIPCO_OTP_SWSIGN_OFF (-2)
564 #define SSB_CHIPCO_OTP_CIDSIGN_OFF (-1)
580 * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU)
601 return (cc->dev != NULL); in ssb_chipco_available()
605 #define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset)
606 #define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val)