Lines Matching +full:0 +full:x60

10 #define SDW_SHIM_BASE			0x2C000
11 #define SDW_ALH_BASE			0x2C800
12 #define SDW_SHIM_BASE_ACE		0x38000
13 #define SDW_ALH_BASE_ACE		0x24000
14 #define SDW_LINK_BASE			0x30000
15 #define SDW_LINK_SIZE			0x10000
19 #define SDW_SHIM_LCAP			0x0
20 #define SDW_SHIM_LCAP_LCOUNT_MASK	GENMASK(2, 0)
23 #define SDW_SHIM_LCTL			0x4
25 #define SDW_SHIM_LCTL_SPA		BIT(0)
26 #define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
31 #define SDW_SHIM_SYNC			0xC
35 #define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
42 #define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
43 #define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
44 #define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
45 #define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
46 #define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
49 #define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
51 #define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
56 #define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))
59 #define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))
61 #define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
67 #define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
69 #define SDW_SHIM_IOCTL_MIF		BIT(0)
80 #define SDW_SHIM_WAKEEN			0x190
82 #define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
85 #define SDW_SHIM_WAKESTS		0x192
87 #define SDW_SHIM_WAKESTS_STATUS		BIT(0)
90 #define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
92 #define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
97 #define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
100 #define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
101 #define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
165 #define SDW_INTEL_CLK_STOP_NOT_ALLOWED		BIT(0)