Lines Matching +full:clock +full:- +full:master
1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
25 /* SDW Master Device Number, not supported yet */
71 * enum sdw_slave_status - Slave status
85 * enum sdw_clk_stop_type: clock stop operations
87 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare
88 * @SDW_CLK_POST_PREPARE: post clock stop prepare
89 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
90 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
100 * enum sdw_command_response - Command response as defined by SDW spec
186 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
197 * enum sdw_dpn_type - Data port types
212 * enum sdw_clk_stop_mode - Clock Stop modes
213 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock
215 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
216 * not capable of continuing operation seamlessly when the clock restarts
224 * struct sdw_dp0_prop - DP0 properties
235 * implementation-defined interrupts
252 * struct sdw_dpn_audio_mode - Audio mode properties for DPn
262 * sequence and bus clock configuration
263 * If 0, Channel Prepare can happen at any Bus clock rate
264 * If 1, Channel Prepare sequence shall happen only after Bus clock is
284 * struct sdw_dpn_prop - Data Port DPn properties
297 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
299 * implementation-defined interrupts
340 * struct sdw_slave_prop - SoundWire Slave properties
342 * @wake_capable: Wake-up events are supported
344 * @clk_stop_mode1: Clock-Stop Mode 1 is supported
345 * @simple_clk_stop_capable: Simple clock mode is supported
346 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
348 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
351 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1
357 * @p15_behave: Slave behavior when the Master attempts a read to the Port15
398 * struct sdw_master_prop - Master properties
400 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported
401 * @max_clk_freq: Maximum Bus clock frequency, in Hz
402 * @num_clk_gears: Number of clock gears supported
403 * @clk_gears: Clock gears supported
404 * @num_clk_freq: Number of clock frequencies supported, in Hz
405 * @clk_freq: Clock frequencies supported, in Hz
412 * @mclk_freq: clock reference passed to SoundWire Master, in Hz.
413 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux
434 /* Definitions for Master quirks */
448 * issues at the Master level.
464 * struct sdw_slave_id - Slave ID
482 * Helper macros to extract the MIPI-defined IDs
511 * struct sdw_slave_intr_status - Slave interrupt status
523 * sdw_reg_bank - SoundWire register banks
535 * @clk_freq: Clock frequency, in Hz
548 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
552 * @prepare: Prepare (true) /de-prepare (false) channel
553 * @bank: Register bank, which bank Slave/Master driver should program for
584 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
585 * @curr_dr_freq: Current double rate clock frequency, in Hz
590 * @m_data_mode: NORMAL, STATIC or PRBS mode for all Master ports. The value
615 * @clk_stop: handle imp-def sequences before and after prepare and de-prepare
635 * struct sdw_slave - SoundWire Slave
644 * @m_port_map: static Master port map for each Slave port
646 * @dev_num_sticky: one-time static Device Number assigned by Bus
653 * @unattach_request: mask field to keep track why the Slave re-attached and
654 * was re-initialized. This is useful to deal with potential race conditions
655 * between the Master suspending and the codec resuming, and make sure that
656 * when the Master triggered a reset the Slave is properly enumerated and
690 * struct sdw_master_device - SoundWire 'Master Device' representation
691 * @dev: Linux device for this Master
728 * SDW master structures and APIs
795 * struct sdw_master_port_ops: Callback functions from bus to Master
796 * driver to set Master Data ports.
798 * @dpn_set_port_params: Set the Port parameters for the Master Port.
800 * @dpn_set_port_transport_params: Set transport parameters for the Master
802 * @dpn_port_prep: Port prepare operations for the Master Data Port.
803 * @dpn_port_enable_ch: Enable the channels of Master Port.
821 * struct sdw_defer - SDW deffered message
833 * struct sdw_master_ops - Master driver ops
834 * @read_prop: Read Master properties
865 * struct sdw_bus - SoundWire bus
866 * @dev: Shortcut to &bus->md->dev to avoid changing the entire code.
867 * @md: Master device
868 * @link_id: Link id number, can be 0 to N, unique for each Master
869 * @id: bus system-wide unique id
876 * @ops: Master callback ops
877 * @port_ops: Master port callback ops
879 * @prop: Master properties
880 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This
881 * is used to compute and program bus bandwidth, clock, frame shape,
885 * @clk_stop_timeout: Clock stop timeout computed
891 * hardware-based synchronization is required. This value is only
892 * meaningful if multi_link is set. If set to 1, hardware-based
896 * used to allocate system-unique device numbers. This value needs to be
932 * sdw_port_config: Master or Slave Port configuration
943 * sdw_stream_config: Master or Slave stream configuration
967 * @SDW_STREAM_DEPREPARED: Stream de-prepared
1000 * @master_list: List of Master runtime(s) in this stream.
1001 * master_list can contain only one m_rt per Master instance
1003 * @m_rt_count: Count of Master runtime(s) in this stream