Lines Matching +full:0 +full:x610
75 #define GENI_FORCE_DEFAULT_REG 0x20
76 #define SE_GENI_STATUS 0x40
77 #define GENI_SER_M_CLK_CFG 0x48
78 #define GENI_SER_S_CLK_CFG 0x4c
79 #define GENI_IF_DISABLE_RO 0x64
80 #define GENI_FW_REVISION_RO 0x68
81 #define SE_GENI_CLK_SEL 0x7c
82 #define SE_GENI_DMA_MODE_EN 0x258
83 #define SE_GENI_M_CMD0 0x600
84 #define SE_GENI_M_CMD_CTRL_REG 0x604
85 #define SE_GENI_M_IRQ_STATUS 0x610
86 #define SE_GENI_M_IRQ_EN 0x614
87 #define SE_GENI_M_IRQ_CLEAR 0x618
88 #define SE_GENI_S_CMD0 0x630
89 #define SE_GENI_S_CMD_CTRL_REG 0x634
90 #define SE_GENI_S_IRQ_STATUS 0x640
91 #define SE_GENI_S_IRQ_EN 0x644
92 #define SE_GENI_S_IRQ_CLEAR 0x648
93 #define SE_GENI_TX_FIFOn 0x700
94 #define SE_GENI_RX_FIFOn 0x780
95 #define SE_GENI_TX_FIFO_STATUS 0x800
96 #define SE_GENI_RX_FIFO_STATUS 0x804
97 #define SE_GENI_TX_WATERMARK_REG 0x80c
98 #define SE_GENI_RX_WATERMARK_REG 0x810
99 #define SE_GENI_RX_RFR_WATERMARK_REG 0x814
100 #define SE_GENI_IOS 0x908
101 #define SE_DMA_TX_IRQ_STAT 0xc40
102 #define SE_DMA_TX_IRQ_CLR 0xc44
103 #define SE_DMA_TX_FSM_RST 0xc58
104 #define SE_DMA_RX_IRQ_STAT 0xd40
105 #define SE_DMA_RX_IRQ_CLR 0xd44
106 #define SE_DMA_RX_FSM_RST 0xd58
107 #define SE_HW_PARAM_0 0xe24
108 #define SE_HW_PARAM_1 0xe28
111 #define FORCE_DEFAULT BIT(0)
114 #define M_GENI_CMD_ACTIVE BIT(0)
118 #define SER_CLK_EN BIT(0)
123 #define FIFO_IF_DISABLE (BIT(0))
130 #define CLK_SEL_MSK GENMASK(2, 0)
133 #define GENI_DMA_MODE_EN BIT(0)
138 #define M_PARAMS_MSK GENMASK(26, 0)
143 #define M_GENI_DISABLE BIT(0)
148 #define S_PARAMS_MSK GENMASK(26, 0)
153 #define S_GENI_DISABLE BIT(0)
156 #define M_CMD_DONE_EN BIT(0)
188 #define S_CMD_DONE_EN BIT(0)
211 #define WATERMARK_MSK GENMASK(5, 0)
214 #define TX_FIFO_WC GENMASK(27, 0)
220 #define RX_FIFO_WC_MSK GENMASK(24, 0)
224 #define RX_DATA_IN BIT(0)
227 #define TX_DMA_DONE BIT(0)
233 #define RX_DMA_DONE BIT(0)
258 #define HW_VER_STEP_MASK GENMASK(15, 0)
265 #define QUP_SE_VERSION_2_5 0x20050000