Lines Matching full:transmit
63 #define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */
71 #define SSCR1_TIE BIT(1) /* Transmit FIFO Interrupt Enable */
75 #define SSCR1_MWDS BIT(5) /* Microwire Transmit Data Size */
78 #define SSSR_TNF BIT(2) /* Transmit FIFO Not Full */
81 #define SSSR_TFS BIT(5) /* Transmit FIFO Service Request */
88 #define SSSR_TFL_MASK GENMASK(11, 8) /* Transmit FIFO Level mask */
91 #define SSCR1_TFT GENMASK(9, 6) /* Transmit FIFO Threshold (mask) */
99 #define CE4100_SSSR_TFL_MASK GENMASK(9, 8) /* Transmit FIFO Level mask */
102 #define CE4100_SSCR1_TFT GENMASK(7, 6) /* Transmit FIFO Threshold (mask) */
119 #define QUARK_X1000_SSSR_TFL_MASK GENMASK(12, 8) /* Transmit FIFO Level mask */
122 #define QUARK_X1000_SSCR1_TFT GENMASK(10, 6) /* Transmit FIFO Threshold (mask) */
139 #define SSCR1_TSRE BIT(21) /* Transmit Service Request Enable */
141 #define SSCR1_RWOT BIT(23) /* Receive Without Transmit */
154 #define SSSR_TUR BIT(21) /* Transmit FIFO Under Run */
193 #define SFIFOL_TFL_MASK GENMASK(15, 0) /* Transmit FIFO Level mask */
196 #define SFIFOTT_TFT GENMASK(15, 0) /* Transmit FIFO Threshold (mask) */