Lines Matching +full:enable +full:- +full:extended +full:- +full:delay
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
56 #define SSCR0_SSE BIT(7) /* Synchronous Serial Port Enable */
60 #define SSCR0_EDSS BIT(20) /* Extended data size select */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
66 #define SSCR0_FPCKE BIT(29) /* FIFO packing enable */
70 #define SSCR1_RIE BIT(0) /* Receive FIFO Interrupt Enable */
71 #define SSCR1_TIE BIT(1) /* Transmit FIFO Interrupt Enable */
72 #define SSCR1_LBM BIT(2) /* Loop-Back Mode */
92 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
94 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
103 #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
105 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
112 #define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */
123 #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */
125 #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */
126 #define QUARK_X1000_SSCR1_EFWR BIT(16) /* Enable FIFO Write/Read */
131 #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
133 #define SSCR1_EFWR BIT(14) /* Enable FIFO Write/Read */
136 #define SSCR1_PINTE BIT(18) /* Peripheral Trailing Byte Interrupt Enable */
137 #define SSCR1_TINTE BIT(19) /* Receiver Time-out Interrupt enable */
138 #define SSCR1_RSRE BIT(20) /* Receive Service Request Enable */
139 #define SSCR1_TSRE BIT(21) /* Transmit Service Request Enable */
144 #define SSCR1_ECRB BIT(26) /* Enable Clock request B */
145 #define SSCR1_ECRA BIT(27) /* Enable Clock Request A */
147 #define SSCR1_EBCEI BIT(29) /* Enable Bit Count Error interrupt */
148 #define SSCR1_TTE BIT(30) /* TXD Tristate Enable */
149 #define SSCR1_TTELP BIT(31) /* TXD Tristate Enable Last Phase */
152 #define SSSR_TINT BIT(19) /* Receiver Time-out Interrupt */
161 #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
163 #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
169 #define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
170 #define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */
197 #define SFIFOTT_TxThresh(x) (((x) - 1) << 0) /* TX FIFO trigger threshold / level */
199 #define SFIFOTT_RxThresh(x) (((x) - 1) << 16) /* RX FIFO trigger threshold / level */
203 #define SSITF_TxHiThresh(x) (((x) - 1) << 0)
204 #define SSITF_TxLoThresh(x) (((x) - 1) << 8)
207 #define SSIRF_RxThresh(x) ((x) - 1)
252 * pxa_ssp_write_reg - Write to a SSP register
260 __raw_writel(val, dev->mmio_base + reg); in pxa_ssp_write_reg()
264 * pxa_ssp_read_reg - Read from a SSP register
271 return __raw_readl(dev->mmio_base + reg); in pxa_ssp_read_reg()