Lines Matching +full:cs +full:- +full:setup
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
59 u32 access; /* Start-cycle to first data valid delay */
78 u32 t_ceasu; /* address setup to CS valid */
79 u32 t_avdasu; /* address setup to ADV valid */
90 u32 t_oeasu; /* address setup to OE valid */
94 u32 t_ce; /* access time from CS asertion */
96 u32 t_cez_r; /* read CS deassertion to high Z */
97 u32 t_cez_w; /* write CS deassertion to high Z */
99 u32 t_weasu; /* address setup to WE valid */
106 u32 t_ces; /* CS setup time to clk */
107 u32 t_avds; /* ADV setup time to clk */
113 u32 t_ce_avd; /* CS on to ADV on delay */
134 #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
135 #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
136 #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
137 #define GPMC_MUX_AD 2 /* Addr-Data multiplex */
151 u32 wait_pin; /* wait-pin to be used */
157 bool is_nand; /* device within this CS is NAND */
161 struct platform_device *pdev; /* device within this CS region */
166 struct gpmc_omap_cs_data cs[GPMC_CS_NUM]; member