Lines Matching defs:pci_dev
321 struct pci_dev { struct
344 struct pci_dev *rcec; /* Associated RCEC device */ argument
346 u32 devcap; /* PCIe Device Capabilities */
347 u8 pcie_cap; /* PCIe capability offset */
348 u8 msi_cap; /* MSI capability offset */
349 u8 msix_cap; /* MSI-X capability offset */
350 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
351 u8 rom_base_reg; /* Config register controlling ROM */
352 u8 pin; /* Interrupt pin this device uses */
353 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
354 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
356 struct pci_driver *driver; /* Driver bound to this device */
357 u64 dma_mask; /* Mask of the bits of bus address this
363 struct device_dma_parameters dma_parms;
365 pci_power_t current_state; /* Current operating state. In ACPI,
368 unsigned int imm_ready:1; /* Supports Immediate Readiness */
369 u8 pm_cap; /* PM capability offset */
370 unsigned int pme_support:5; /* Bitmask of states from which PME#
372 unsigned int pme_poll:1; /* Poll device's PME status bit */
373 unsigned int d1_support:1; /* Low power state D1 is supported */
374 unsigned int d2_support:1; /* Low power state D2 is supported */
375 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
376 unsigned int no_d3cold:1; /* D3cold is forbidden */
377 unsigned int bridge_d3:1; /* Allow D3 for bridge */
378 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
379 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
381 unsigned int wakeup_prepared:1;
382 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
383 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
384 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
387 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
389 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
390 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
393 struct pcie_link_state *link_state; /* ASPM link state */
394 unsigned int ltr_path:1; /* Latency Tolerance Reporting
396 u16 l1ss; /* L1SS Capability pointer */
398 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
399 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
401 pci_channel_state_t error_state; /* Current connectivity state */
402 struct device dev; /* Generic device interface */
404 int cfg_size; /* Size of config space */
410 unsigned int irq;
411 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
413 bool match_driver; /* Skip attaching driver */
415 unsigned int transparent:1; /* Subtractive decode bridge */
416 unsigned int io_window:1; /* Bridge has I/O window */
417 unsigned int pref_window:1; /* Bridge has pref mem window */
418 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
419 unsigned int multifunction:1; /* Multi-function device */
421 unsigned int is_busmaster:1; /* Is busmaster */
422 unsigned int no_msi:1; /* May not use MSI */
423 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
424 unsigned int block_cfg_access:1; /* Config space access blocked */
425 unsigned int broken_parity_status:1; /* Generates false positive parity */
426 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
427 unsigned int msi_enabled:1;
428 unsigned int msix_enabled:1;
429 unsigned int ari_enabled:1; /* ARI forwarding */
430 unsigned int ats_enabled:1; /* Address Translation Svc */
431 unsigned int pasid_enabled:1; /* Process Address Space ID */
432 unsigned int pri_enabled:1; /* Page Request Interface */
433 unsigned int is_managed:1; /* Managed via devres */
434 unsigned int is_msi_managed:1; /* MSI release via devres installed */
435 unsigned int needs_freset:1; /* Requires fundamental reset */
436 unsigned int state_saved:1;
437 unsigned int is_physfn:1;
438 unsigned int is_virtfn:1;
439 unsigned int is_hotplug_bridge:1;
440 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
441 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
465 pci_dev_flags_t dev_flags; argument
466 atomic_t enable_cnt; /* pci_enable_device has been called */
468 u32 saved_config_space[16]; /* Config space saved at suspend time */
469 struct hlist_head saved_cap_space;
470 int rom_attr_enabled; /* Display of ROM attribute enabled? */
471 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
472 …uct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
496 struct pci_dev *physfn; /* VF: related PF */ argument
498 u16 ats_cap; /* ATS Capability offset */
499 u8 ats_stu; /* ATS Smallest Translation Unit */
502 u16 pri_cap; /* PRI Capability offset */
503 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
504 unsigned int pasid_required:1; /* PRG Response PASID Required */
528 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) in pci_physfn() argument
722 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) in pci_dev_msi_enabled()
727 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } in pci_dev_msi_enabled()