1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8  *	Contains standard defines and IDs for NAND flash devices
17 #include <linux/mtd/nand.h>
29 /* The maximum number of NAND chips in an array */
50  * Standard NAND flash commands
73 #define NAND_CMD_NONE		-1
82 #define NAND_DATA_IFACE_CHECK_ONLY	-1
85  * Constants for Hardware ECC
87 /* Reset Hardware ECC for read */
89 /* Reset Hardware ECC for write */
91 /* Enable Hardware ECC before syndrome is read back from flash */
95  * Enable generic NAND 'page erased' check. This check is only done when
96  * ecc.correct() returns -EBADMSG.
122  * Chip requires ready check on read (for auto-incremented sequential read).
131 /* Device is one of 'new' xD cards that expose fake nand command set */
134 /* Device behaves just like nand, but is readonly */
140 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
158  * Autodetect nand buswidth with readid/onfi.
159  * This suppose the driver will configure the hardware in 8 bits mode
172  * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
173  * on the default ->cmdfunc() implementation, you may want to let the core
182  * Whether the NAND chip is a boot medium. Drivers might use this information
183  * to select ECC algorithms supported by the boot ROM or similar restrictions.
206  * Some controllers with pipelined ECC engines override the BBM marker with
207  * data or ECC bytes, thus making bad block detection through bad block marker
223  * struct nand_parameters - NAND generic parameters from the parameter page
225  * @supports_set_get_features: The NAND chip supports setting/getting features
241 /* The maximum expected count of bytes in the NAND ID sequence */
245  * struct nand_id - NAND id structure
255  * struct nand_ecc_step_info - ECC step information of ECC engine
256  * @stepsize: data bytes per ECC step
267  * struct nand_ecc_caps - capability of ECC engine
268  * @stepinfos: array of ECC step information
269  * @nstepinfos: number of ECC step information
270  * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
278 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
293  * struct nand_ecc_ctrl - Control structure for ECC
294  * @engine_type: ECC engine type
296  * @algo:	ECC algorithm
297  * @steps:	number of ECC steps per page
298  * @size:	data bytes per ECC step
299  * @bytes:	ECC bytes per step
300  * @strength:	max number of correctible bits per ECC step
301  * @total:	total number of ECC bytes per page
302  * @prepad:	padding information for syndrome based ECC generators
303  * @postpad:	padding information for syndrome based ECC generators
304  * @options:	ECC specific options (see NAND_ECC_XXX flags defined above)
305  * @calc_buf:	buffer for calculated ECC, size is oobsize.
306  * @code_buf:	buffer for ECC read from flash, size is oobsize.
307  * @hwctl:	function to control hardware ECC generator. Must only
308  *		be provided if an hardware ECC is available
309  * @calculate:	function for ECC calculation or readback from ECC hardware
310  * @correct:	function for ECC correction, matching to ECC generator (sw/hw).
312  *		corrected bitflips, -EBADMSG if the number of bitflips exceed
313  *		ECC strength, or any other error code if the error is not
315  *		If -EBADMSG is returned the input buffers should be left
317  * @read_page_raw:	function to read a raw page without ECC. This function
318  *			should hide the specific layout used by the ECC
319  *			controller and always return contiguous in-band and
320  *			out-of-band data even if they're not stored
321  *			contiguously on the NAND chip (e.g.
322  *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
323  *			out-of-band data).
324  * @write_page_raw:	function to write a raw page without ECC. This function
325  *			should hide the specific layout used by the ECC
327  *			in-band and out-of-band data. ECC controller is
330  *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
331  *			out-of-band data).
332  * @read_page:	function to read a page according to the ECC generator
334  *		any single ECC step, -EIO hw error
335  * @read_subpage:	function to read parts of the page covered by ECC;
337  * @write_subpage:	function to write parts of the page covered by ECC.
338  * @write_page:	function to write a page according to the ECC generator
340  * @write_oob_raw:	function to write chip OOB data without ECC
341  * @read_oob_raw:	function to read chip OOB data without ECC
359 	void (*hwctl)(struct nand_chip *chip, int mode);
384  * struct nand_sdr_timings - SDR NAND chip timings
386  * This struct defines the timing requirements of a SDR NAND chip.
387  * These information can be found in every NAND datasheets and the timings
389  * https://media-www.micron.com/-/media/client/onfi/specs/onfi_3_1_spec.pdf
405  * @tCHZ_max: CE# high to output hi-Z
414  * @tIR_min: Output hi-Z to RE# low
415  * @tITC_max: Interface and Timing Mode Change time
421  * @tRHZ_max: RE# high to output hi-Z
476  * struct nand_nvddr_timings - NV-DDR NAND chip timings
478  * This struct defines the timing requirements of a NV-DDR NAND data interface.
479  * These information can be found in every NAND datasheets and the timings
481  * https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf
482  * (chapter 4.18.2 NV-DDR)
507  * @tDQSHZ_max: W/R_n high to DQS/DQ tri-state by device
508  * @tDQSQ_max: DQS-DQ skew, DQS to last DQ valid, per access
512  * @tITC_max: Interface and Timing Mode Change time
563  * between SDR and NV-DDR, timings related to the internal chip behavior are
565  * the same definition and are shared in both SDR and NV-DDR timing structures:
566  * - tADL_min
567  * - tBERS_max
568  * - tCCS_min
569  * - tFEAT_max
570  * - tPROG_max
571  * - tR_max
572  * - tRR_min
573  * - tRST_max
574  * - tWB_max
580 		nand_get_sdr_timings(conf)->timing_name :	\
581 		nand_get_nvddr_timings(conf)->timing_name
590  * enum nand_interface_type - NAND interface type
600  * struct nand_interface_config - NAND interface timing
603  * @timings.mode: Timing mode as defined in the specification
610 		unsigned int mode;  member
619  * nand_interface_is_sdr - get the interface type
624 	return conf->type == NAND_SDR_IFACE;  in nand_interface_is_sdr()
628  * nand_interface_is_nvddr - get the interface type
633 	return conf->type == NAND_NVDDR_IFACE;  in nand_interface_is_nvddr()
637  * nand_get_sdr_timings - get SDR timing from data interface
644 		return ERR_PTR(-EINVAL);  in nand_get_sdr_timings()
646 	return &conf->timings.sdr;  in nand_get_sdr_timings()
650  * nand_get_nvddr_timings - get NV-DDR timing from data interface
657 		return ERR_PTR(-EINVAL);  in nand_get_nvddr_timings()
659 	return &conf->timings.nvddr;  in nand_get_nvddr_timings()
663  * struct nand_op_cmd_instr - Definition of a command instruction
671  * struct nand_op_addr_instr - Definition of an address instruction
681  * struct nand_op_data_instr - Definition of a data instruction
684  * @buf.in: buffer to fill when reading from the NAND chip
685  * @buf.out: buffer to read from when writing to the NAND chip
686  * @force_8bit: force 8-bit access
689  * and are from the controller perspective, so a "in" is a read from the NAND
690  * chip while a "out" is a write to the NAND chip.
702  * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
710  * enum nand_op_instr_type - Definition of all instruction types
726  * struct nand_op_instr - Instruction object
841  * struct nand_subop - a sub operation
842  * @cs: the CS line to select for this NAND sub-operation
846  *			   of the sub-operation
848  *			of the sub-operation
853  * When an operation cannot be handled as is by the NAND controller, it will
854  * be split by the parser into sub-operations which will be passed to the
875  * struct nand_op_parser_addr_constraints - Constraints for address instructions
884  * struct nand_op_parser_data_constraints - Constraints for data instructions
892  * struct nand_op_parser_pattern_elem - One element of a pattern
942  * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
945  * @exec: the function that will issue a sub-operation
948  * with its constraints. The pattern itself is used by the core to match NAND
949  * chip operation with NAND controller operations.
950  * Once a match between a NAND controller operation pattern and a NAND chip
951  * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
974  * struct nand_op_parser - NAND controller operation parser descriptor
980  * NAND operation (or tries to determine if a specific operation is supported).
1000  * struct nand_operation - NAND operation descriptor
1001  * @cs: the CS line to select for this NAND operation
1005  * The actual operation structure that will be passed to chip->exec_op().
1028 	switch (instr->type) {  in nand_op_trace()
1031 			 instr->ctx.cmd.opcode);  in nand_op_trace()
1035 			 instr->ctx.addr.naddrs,  in nand_op_trace()
1036 			 instr->ctx.addr.naddrs < 64 ?  in nand_op_trace()
1037 			 instr->ctx.addr.naddrs : 64,  in nand_op_trace()
1038 			 instr->ctx.addr.addrs);  in nand_op_trace()
1042 			 instr->ctx.data.len,  in nand_op_trace()
1043 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
1044 			 ", force 8-bit" : "");  in nand_op_trace()
1048 			 instr->ctx.data.len,  in nand_op_trace()
1049 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
1050 			 ", force 8-bit" : "");  in nand_op_trace()
1054 			 instr->ctx.waitrdy.timeout_ms);  in nand_op_trace()
1061  * struct nand_controller_ops - Controller operations
1063  * @attach_chip: this method is called after the NAND detection phase after
1065  *		 size have been set up. ECC requirements are available if
1066  *		 provided by the NAND chip or device tree. Typically used to
1067  *		 choose the appropriate ECC configuration and allocate
1071  *		 nand_controller_ops->attach_chip().
1073  * @exec_op:	 controller specific method to execute NAND operations.
1074  *		 This method replaces chip->legacy.cmdfunc(),
1075  *		 chip->legacy.{read,write}_{buf,byte,word}(),
1076  *		 chip->legacy.dev_ready() and chip->legacy.waifunc().
1093  * struct nand_controller - Structure used to describe a NAND controller
1095  * @lock:		lock used to serialize accesses to the NAND controller
1096  * @ops:		NAND controller operations.
1105 	mutex_init(&nfc->lock);  in nand_controller_init()
1109  * struct nand_legacy - NAND chip legacy fields/hooks
1126  * @set_features: set the NAND chip features
1127  * @get_features: get the NAND chip features
1160  * struct nand_chip_ops - NAND chip operations
1165  * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs)
1179  * struct nand_manufacturer - NAND manufacturer structure
1189  * struct nand_secure_region - NAND secure region structure
1199  * struct nand_chip - NAND Private Flash Chip Data
1200  * @base: Inherit from the generic NAND device
1201  * @id: Holds NAND ID
1204  * @ops: NAND chip operations
1212  * @current_interface_config: The currently used NAND interface configuration
1213  * @best_interface_config: The best NAND interface configuration which fits both
1214  *                         the NAND chip and NAND controller constraints. If
1231  * @pagemask: Page number mask = number of (pages / chip) - 1
1237  * @pagecache.page: Page number currently in the cache. -1 means no page is
1241  *        to the NAND device
1244  * @cur_cs: Currently selected target. -1 means no target selected, otherwise we
1246  *          NAND Controller drivers should not modify this value, but they're
1253  * @ecc: The ECC controller structure
1306 	struct nand_ecc_ctrl ecc;  member
1317 	return &chip->base.mtd;  in nand_to_mtd()
1322 	return chip->priv;  in nand_get_controller_data()
1327 	chip->priv = priv;  in nand_set_controller_data()
1333 	chip->manufacturer.priv = priv;  in nand_set_manufacturer_data()
1338 	return chip->manufacturer.priv;  in nand_get_manufacturer_data()
1353  * nand_get_interface_config - Retrieve the current interface configuration
1354  *                             of a NAND chip
1355  * @chip: The NAND chip
1360 	return chip->current_interface_config;  in nand_get_interface_config()
1364  * A helper for defining older NAND chips where the second ID byte fully
1366  * size). All these chips have 512 bytes NAND page size.
1388 #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
1389 #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
1392  * struct nand_flash_dev - NAND Flash Device ID Structure
1393  * @name: a human-readable name of the NAND chip
1400  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1401  *            well as the eraseblock size) is determined from the extended NAND
1408  * @ecc: ECC correctability and step information from the datasheet.
1409  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1411  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1413  *               For example, the "4bit ECC for each 512Byte" can be set with
1434 	} ecc;  member
1440  * Check if it is a SLC nand.
1441  * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1446 	WARN(nanddev_bits_per_cell(&chip->base) == 0,  in nand_is_slc()
1447 	     "chip->bits_per_cell is used uninitialized\n");  in nand_is_slc()
1448 	return nanddev_bits_per_cell(&chip->base) == 1;  in nand_is_slc()
1452  * nand_opcode_8bits - Check if the opcode's address should be sent only on the
1485 				void *ecc, int ecclen,
1514 /* Reset and initialize a NAND device */
1517 /* NAND operation helpers */
1547 /* Scan and identify a NAND device */
1560  * Free resources held by the NAND device, must be called on error after a
1573 /* Select/deselect a NAND target. */
1582  * nand_get_data_buf() - Get the internal page buffer
1583  * @chip: NAND chip object
1585  * Returns the pre-allocated page buffer after invalidating the cache. This
1597 	chip->pagecache.page = -1;  in nand_get_data_buf()
1599 	return chip->data_buf;  in nand_get_data_buf()
1602 /* Parse the gpio-cs property */