1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5  *		          Thomas Gleixner <tglx@linutronix.de>
73 #define NAND_CMD_NONE		-1
82 #define NAND_DATA_IFACE_CHECK_ONLY	-1
96  * ecc.correct() returns -EBADMSG.
122  * Chip requires ready check on read (for auto-incremented sequential read).
140 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
172  * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
173  * on the default ->cmdfunc() implementation, you may want to let the core
223  * struct nand_parameters - NAND generic parameters from the parameter page
245  * struct nand_id - NAND id structure
255  * struct nand_ecc_step_info - ECC step information of ECC engine
267  * struct nand_ecc_caps - capability of ECC engine
293  * struct nand_ecc_ctrl - Control structure for ECC
312  *		corrected bitflips, -EBADMSG if the number of bitflips exceed
315  *		If -EBADMSG is returned the input buffers should be left
319  *			controller and always return contiguous in-band and
320  *			out-of-band data even if they're not stored
322  *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
323  *			out-of-band data).
327  *			in-band and out-of-band data. ECC controller is
330  *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
331  *			out-of-band data).
334  *		any single ECC step, -EIO hw error
384  * struct nand_sdr_timings - SDR NAND chip timings
389  * https://media-www.micron.com/-/media/client/onfi/specs/onfi_3_1_spec.pdf
405  * @tCHZ_max: CE# high to output hi-Z
414  * @tIR_min: Output hi-Z to RE# low
421  * @tRHZ_max: RE# high to output hi-Z
476  * struct nand_nvddr_timings - NV-DDR NAND chip timings
478  * This struct defines the timing requirements of a NV-DDR NAND data interface.
481  * https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf
482  * (chapter 4.18.2 NV-DDR)
507  * @tDQSHZ_max: W/R_n high to DQS/DQ tri-state by device
508  * @tDQSQ_max: DQS-DQ skew, DQS to last DQ valid, per access
513  * @tQHS_max: Data hold skew factor
563  * between SDR and NV-DDR, timings related to the internal chip behavior are
565  * the same definition and are shared in both SDR and NV-DDR timing structures:
566  * - tADL_min
567  * - tBERS_max
568  * - tCCS_min
569  * - tFEAT_max
570  * - tPROG_max
571  * - tR_max
572  * - tRR_min
573  * - tRST_max
574  * - tWB_max
580 		nand_get_sdr_timings(conf)->timing_name :	\
581 		nand_get_nvddr_timings(conf)->timing_name
590  * enum nand_interface_type - NAND interface type
600  * struct nand_interface_config - NAND interface timing
619  * nand_interface_is_sdr - get the interface type
624 	return conf->type == NAND_SDR_IFACE;  in nand_interface_is_sdr()
628  * nand_interface_is_nvddr - get the interface type
633 	return conf->type == NAND_NVDDR_IFACE;  in nand_interface_is_nvddr()
637  * nand_get_sdr_timings - get SDR timing from data interface
644 		return ERR_PTR(-EINVAL);  in nand_get_sdr_timings()
646 	return &conf->timings.sdr;  in nand_get_sdr_timings()
650  * nand_get_nvddr_timings - get NV-DDR timing from data interface
657 		return ERR_PTR(-EINVAL);  in nand_get_nvddr_timings()
659 	return &conf->timings.nvddr;  in nand_get_nvddr_timings()
663  * struct nand_op_cmd_instr - Definition of a command instruction
671  * struct nand_op_addr_instr - Definition of an address instruction
681  * struct nand_op_data_instr - Definition of a data instruction
686  * @force_8bit: force 8-bit access
702  * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
710  * enum nand_op_instr_type - Definition of all instruction types
726  * struct nand_op_instr - Instruction object
841  * struct nand_subop - a sub operation
842  * @cs: the CS line to select for this NAND sub-operation
846  *			   of the sub-operation
848  *			of the sub-operation
854  * be split by the parser into sub-operations which will be passed to the
875  * struct nand_op_parser_addr_constraints - Constraints for address instructions
884  * struct nand_op_parser_data_constraints - Constraints for data instructions
892  * struct nand_op_parser_pattern_elem - One element of a pattern
942  * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
945  * @exec: the function that will issue a sub-operation
951  * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
974  * struct nand_op_parser - NAND controller operation parser descriptor
1000  * struct nand_operation - NAND operation descriptor
1005  * The actual operation structure that will be passed to chip->exec_op().
1028 	switch (instr->type) {  in nand_op_trace()
1031 			 instr->ctx.cmd.opcode);  in nand_op_trace()
1035 			 instr->ctx.addr.naddrs,  in nand_op_trace()
1036 			 instr->ctx.addr.naddrs < 64 ?  in nand_op_trace()
1037 			 instr->ctx.addr.naddrs : 64,  in nand_op_trace()
1038 			 instr->ctx.addr.addrs);  in nand_op_trace()
1042 			 instr->ctx.data.len,  in nand_op_trace()
1043 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
1044 			 ", force 8-bit" : "");  in nand_op_trace()
1048 			 instr->ctx.data.len,  in nand_op_trace()
1049 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
1050 			 ", force 8-bit" : "");  in nand_op_trace()
1054 			 instr->ctx.waitrdy.timeout_ms);  in nand_op_trace()
1061  * struct nand_controller_ops - Controller operations
1071  *		 nand_controller_ops->attach_chip().
1074  *		 This method replaces chip->legacy.cmdfunc(),
1075  *		 chip->legacy.{read,write}_{buf,byte,word}(),
1076  *		 chip->legacy.dev_ready() and chip->legacy.waifunc().
1093  * struct nand_controller - Structure used to describe a NAND controller
1105 	mutex_init(&nfc->lock);  in nand_controller_init()
1109  * struct nand_legacy - NAND chip legacy fields/hooks
1160  * struct nand_chip_ops - NAND chip operations
1165  * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs)
1179  * struct nand_manufacturer - NAND manufacturer structure
1189  * struct nand_secure_region - NAND secure region structure
1199  * struct nand_chip - NAND Private Flash Chip Data
1231  * @pagemask: Page number mask = number of (pages / chip) - 1
1237  * @pagecache.page: Page number currently in the cache. -1 means no page is
1244  * @cur_cs: Currently selected target. -1 means no target selected, otherwise we
1317 	return &chip->base.mtd;  in nand_to_mtd()
1322 	return chip->priv;  in nand_get_controller_data()
1327 	chip->priv = priv;  in nand_set_controller_data()
1333 	chip->manufacturer.priv = priv;  in nand_set_manufacturer_data()
1338 	return chip->manufacturer.priv;  in nand_get_manufacturer_data()
1353  * nand_get_interface_config - Retrieve the current interface configuration
1360 	return chip->current_interface_config;  in nand_get_interface_config()
1388 #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
1389 #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
1392  * struct nand_flash_dev - NAND Flash Device ID Structure
1393  * @name: a human-readable name of the NAND chip
1446 	WARN(nanddev_bits_per_cell(&chip->base) == 0,  in nand_is_slc()
1447 	     "chip->bits_per_cell is used uninitialized\n");  in nand_is_slc()
1448 	return nanddev_bits_per_cell(&chip->base) == 1;  in nand_is_slc()
1452  * nand_opcode_8bits - Check if the opcode's address should be sent only on the
1582  * nand_get_data_buf() - Get the internal page buffer
1585  * Returns the pre-allocated page buffer after invalidating the cache. This
1597 	chip->pagecache.page = -1;  in nand_get_data_buf()
1599 	return chip->data_buf;  in nand_get_data_buf()
1602 /* Parse the gpio-cs property */