Lines Matching +full:0 +full:x18
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
71 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25,
75 MLX5_SHARED_RESOURCE_UID = 0xffff,
79 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
90 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
91 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
92 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
93 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
94 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
95 MLX5_OBJ_TYPE_MKEY = 0xff01,
96 MLX5_OBJ_TYPE_QP = 0xff02,
97 MLX5_OBJ_TYPE_PSV = 0xff03,
98 MLX5_OBJ_TYPE_RMP = 0xff04,
99 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
100 MLX5_OBJ_TYPE_RQ = 0xff06,
101 MLX5_OBJ_TYPE_SQ = 0xff07,
102 MLX5_OBJ_TYPE_TIR = 0xff08,
103 MLX5_OBJ_TYPE_TIS = 0xff09,
104 MLX5_OBJ_TYPE_DCT = 0xff0a,
105 MLX5_OBJ_TYPE_XRQ = 0xff0b,
106 MLX5_OBJ_TYPE_RQT = 0xff0e,
107 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
108 MLX5_OBJ_TYPE_CQ = 0xff10,
112 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
113 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
114 MLX5_CMD_OP_INIT_HCA = 0x102,
115 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
116 MLX5_CMD_OP_ENABLE_HCA = 0x104,
117 MLX5_CMD_OP_DISABLE_HCA = 0x105,
118 MLX5_CMD_OP_QUERY_PAGES = 0x107,
119 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
120 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
121 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
122 MLX5_CMD_OP_SET_ISSI = 0x10b,
123 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
124 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
125 MLX5_CMD_OP_ALLOC_SF = 0x113,
126 MLX5_CMD_OP_DEALLOC_SF = 0x114,
127 MLX5_CMD_OP_SUSPEND_VHCA = 0x115,
128 MLX5_CMD_OP_RESUME_VHCA = 0x116,
129 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117,
130 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118,
131 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119,
132 MLX5_CMD_OP_CREATE_MKEY = 0x200,
133 MLX5_CMD_OP_QUERY_MKEY = 0x201,
134 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
135 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
136 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
137 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
138 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
139 MLX5_CMD_OP_MODIFY_MEMIC = 0x207,
140 MLX5_CMD_OP_CREATE_EQ = 0x301,
141 MLX5_CMD_OP_DESTROY_EQ = 0x302,
142 MLX5_CMD_OP_QUERY_EQ = 0x303,
143 MLX5_CMD_OP_GEN_EQE = 0x304,
144 MLX5_CMD_OP_CREATE_CQ = 0x400,
145 MLX5_CMD_OP_DESTROY_CQ = 0x401,
146 MLX5_CMD_OP_QUERY_CQ = 0x402,
147 MLX5_CMD_OP_MODIFY_CQ = 0x403,
148 MLX5_CMD_OP_CREATE_QP = 0x500,
149 MLX5_CMD_OP_DESTROY_QP = 0x501,
150 MLX5_CMD_OP_RST2INIT_QP = 0x502,
151 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
152 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
153 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
154 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
155 MLX5_CMD_OP_2ERR_QP = 0x507,
156 MLX5_CMD_OP_2RST_QP = 0x50a,
157 MLX5_CMD_OP_QUERY_QP = 0x50b,
158 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
159 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
160 MLX5_CMD_OP_CREATE_PSV = 0x600,
161 MLX5_CMD_OP_DESTROY_PSV = 0x601,
162 MLX5_CMD_OP_CREATE_SRQ = 0x700,
163 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
164 MLX5_CMD_OP_QUERY_SRQ = 0x702,
165 MLX5_CMD_OP_ARM_RQ = 0x703,
166 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
167 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
168 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
169 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
170 MLX5_CMD_OP_CREATE_DCT = 0x710,
171 MLX5_CMD_OP_DESTROY_DCT = 0x711,
172 MLX5_CMD_OP_DRAIN_DCT = 0x712,
173 MLX5_CMD_OP_QUERY_DCT = 0x713,
174 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
175 MLX5_CMD_OP_CREATE_XRQ = 0x717,
176 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
177 MLX5_CMD_OP_QUERY_XRQ = 0x719,
178 MLX5_CMD_OP_ARM_XRQ = 0x71a,
179 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
180 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
181 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
182 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
183 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
184 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
185 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
186 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
187 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
188 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
189 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
190 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
191 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
192 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
193 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
194 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
195 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
196 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
197 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
198 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
199 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
200 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
201 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
202 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
203 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
204 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
205 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
206 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
207 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
208 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
209 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
210 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
211 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
212 MLX5_CMD_OP_ALLOC_PD = 0x800,
213 MLX5_CMD_OP_DEALLOC_PD = 0x801,
214 MLX5_CMD_OP_ALLOC_UAR = 0x802,
215 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
216 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
217 MLX5_CMD_OP_ACCESS_REG = 0x805,
218 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
219 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
220 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
221 MLX5_CMD_OP_MAD_IFC = 0x50d,
222 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
223 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
224 MLX5_CMD_OP_NOP = 0x80d,
225 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
226 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
227 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
228 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
229 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
230 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
231 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
232 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
233 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
234 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
235 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
236 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
237 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
238 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
239 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
240 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
241 MLX5_CMD_OP_CREATE_LAG = 0x840,
242 MLX5_CMD_OP_MODIFY_LAG = 0x841,
243 MLX5_CMD_OP_QUERY_LAG = 0x842,
244 MLX5_CMD_OP_DESTROY_LAG = 0x843,
245 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
246 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
247 MLX5_CMD_OP_CREATE_TIR = 0x900,
248 MLX5_CMD_OP_MODIFY_TIR = 0x901,
249 MLX5_CMD_OP_DESTROY_TIR = 0x902,
250 MLX5_CMD_OP_QUERY_TIR = 0x903,
251 MLX5_CMD_OP_CREATE_SQ = 0x904,
252 MLX5_CMD_OP_MODIFY_SQ = 0x905,
253 MLX5_CMD_OP_DESTROY_SQ = 0x906,
254 MLX5_CMD_OP_QUERY_SQ = 0x907,
255 MLX5_CMD_OP_CREATE_RQ = 0x908,
256 MLX5_CMD_OP_MODIFY_RQ = 0x909,
257 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
258 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
259 MLX5_CMD_OP_QUERY_RQ = 0x90b,
260 MLX5_CMD_OP_CREATE_RMP = 0x90c,
261 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
262 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
263 MLX5_CMD_OP_QUERY_RMP = 0x90f,
264 MLX5_CMD_OP_CREATE_TIS = 0x912,
265 MLX5_CMD_OP_MODIFY_TIS = 0x913,
266 MLX5_CMD_OP_DESTROY_TIS = 0x914,
267 MLX5_CMD_OP_QUERY_TIS = 0x915,
268 MLX5_CMD_OP_CREATE_RQT = 0x916,
269 MLX5_CMD_OP_MODIFY_RQT = 0x917,
270 MLX5_CMD_OP_DESTROY_RQT = 0x918,
271 MLX5_CMD_OP_QUERY_RQT = 0x919,
272 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
273 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
274 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
275 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
276 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
277 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
278 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
279 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
280 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
281 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
282 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
283 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
284 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
285 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
286 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
287 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
288 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
289 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
290 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
291 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
292 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
293 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
294 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
295 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
296 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
297 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
298 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
299 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
300 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
301 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
302 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
303 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
304 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
305 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
306 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
307 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
313 MLX5_CMD_OP_GENERAL_START = 0xb00,
314 MLX5_CMD_OP_GENERAL_END = 0xd00,
318 u8 outer_dmac[0x1];
319 u8 outer_smac[0x1];
320 u8 outer_ether_type[0x1];
321 u8 outer_ip_version[0x1];
322 u8 outer_first_prio[0x1];
323 u8 outer_first_cfi[0x1];
324 u8 outer_first_vid[0x1];
325 u8 outer_ipv4_ttl[0x1];
326 u8 outer_second_prio[0x1];
327 u8 outer_second_cfi[0x1];
328 u8 outer_second_vid[0x1];
329 u8 reserved_at_b[0x1];
330 u8 outer_sip[0x1];
331 u8 outer_dip[0x1];
332 u8 outer_frag[0x1];
333 u8 outer_ip_protocol[0x1];
334 u8 outer_ip_ecn[0x1];
335 u8 outer_ip_dscp[0x1];
336 u8 outer_udp_sport[0x1];
337 u8 outer_udp_dport[0x1];
338 u8 outer_tcp_sport[0x1];
339 u8 outer_tcp_dport[0x1];
340 u8 outer_tcp_flags[0x1];
341 u8 outer_gre_protocol[0x1];
342 u8 outer_gre_key[0x1];
343 u8 outer_vxlan_vni[0x1];
344 u8 outer_geneve_vni[0x1];
345 u8 outer_geneve_oam[0x1];
346 u8 outer_geneve_protocol_type[0x1];
347 u8 outer_geneve_opt_len[0x1];
348 u8 source_vhca_port[0x1];
349 u8 source_eswitch_port[0x1];
351 u8 inner_dmac[0x1];
352 u8 inner_smac[0x1];
353 u8 inner_ether_type[0x1];
354 u8 inner_ip_version[0x1];
355 u8 inner_first_prio[0x1];
356 u8 inner_first_cfi[0x1];
357 u8 inner_first_vid[0x1];
358 u8 reserved_at_27[0x1];
359 u8 inner_second_prio[0x1];
360 u8 inner_second_cfi[0x1];
361 u8 inner_second_vid[0x1];
362 u8 reserved_at_2b[0x1];
363 u8 inner_sip[0x1];
364 u8 inner_dip[0x1];
365 u8 inner_frag[0x1];
366 u8 inner_ip_protocol[0x1];
367 u8 inner_ip_ecn[0x1];
368 u8 inner_ip_dscp[0x1];
369 u8 inner_udp_sport[0x1];
370 u8 inner_udp_dport[0x1];
371 u8 inner_tcp_sport[0x1];
372 u8 inner_tcp_dport[0x1];
373 u8 inner_tcp_flags[0x1];
374 u8 reserved_at_37[0x9];
376 u8 geneve_tlv_option_0_data[0x1];
377 u8 geneve_tlv_option_0_exist[0x1];
378 u8 reserved_at_42[0x3];
379 u8 outer_first_mpls_over_udp[0x4];
380 u8 outer_first_mpls_over_gre[0x4];
381 u8 inner_first_mpls[0x4];
382 u8 outer_first_mpls[0x4];
383 u8 reserved_at_55[0x2];
384 u8 outer_esp_spi[0x1];
385 u8 reserved_at_58[0x2];
386 u8 bth_dst_qp[0x1];
387 u8 reserved_at_5b[0x5];
389 u8 reserved_at_60[0x18];
390 u8 metadata_reg_c_7[0x1];
391 u8 metadata_reg_c_6[0x1];
392 u8 metadata_reg_c_5[0x1];
393 u8 metadata_reg_c_4[0x1];
394 u8 metadata_reg_c_3[0x1];
395 u8 metadata_reg_c_2[0x1];
396 u8 metadata_reg_c_1[0x1];
397 u8 metadata_reg_c_0[0x1];
401 u8 reserved_at_0[0xe];
402 u8 bth_opcode[0x1];
403 u8 reserved_at_f[0x11];
405 u8 reserved_at_20[0x60];
409 u8 ft_support[0x1];
410 u8 reserved_at_1[0x1];
411 u8 flow_counter[0x1];
412 u8 flow_modify_en[0x1];
413 u8 modify_root[0x1];
414 u8 identified_miss_table_mode[0x1];
415 u8 flow_table_modify[0x1];
416 u8 reformat[0x1];
417 u8 decap[0x1];
418 u8 reserved_at_9[0x1];
419 u8 pop_vlan[0x1];
420 u8 push_vlan[0x1];
421 u8 reserved_at_c[0x1];
422 u8 pop_vlan_2[0x1];
423 u8 push_vlan_2[0x1];
424 u8 reformat_and_vlan_action[0x1];
425 u8 reserved_at_10[0x1];
426 u8 sw_owner[0x1];
427 u8 reformat_l3_tunnel_to_l2[0x1];
428 u8 reformat_l2_to_l3_tunnel[0x1];
429 u8 reformat_and_modify_action[0x1];
430 u8 ignore_flow_level[0x1];
431 u8 reserved_at_16[0x1];
432 u8 table_miss_action_domain[0x1];
433 u8 termination_table[0x1];
434 u8 reformat_and_fwd_to_table[0x1];
435 u8 reserved_at_1a[0x2];
436 u8 ipsec_encrypt[0x1];
437 u8 ipsec_decrypt[0x1];
438 u8 sw_owner_v2[0x1];
439 u8 reserved_at_1f[0x1];
441 u8 termination_table_raw_traffic[0x1];
442 u8 reserved_at_21[0x1];
443 u8 log_max_ft_size[0x6];
444 u8 log_max_modify_header_context[0x8];
445 u8 max_modify_header_actions[0x8];
446 u8 max_ft_level[0x8];
448 u8 reserved_at_40[0x6];
449 u8 execute_aso[0x1];
450 u8 reserved_at_47[0x19];
452 u8 reserved_at_60[0x2];
453 u8 reformat_insert[0x1];
454 u8 reformat_remove[0x1];
455 u8 macsec_encrypt[0x1];
456 u8 macsec_decrypt[0x1];
457 u8 reserved_at_66[0x2];
458 u8 reformat_add_macsec[0x1];
459 u8 reformat_remove_macsec[0x1];
460 u8 reserved_at_6a[0xe];
461 u8 log_max_ft_num[0x8];
463 u8 reserved_at_80[0x10];
464 u8 log_max_flow_counter[0x8];
465 u8 log_max_destination[0x8];
467 u8 reserved_at_a0[0x18];
468 u8 log_max_flow[0x8];
470 u8 reserved_at_c0[0x40];
478 u8 send[0x1];
479 u8 receive[0x1];
480 u8 write[0x1];
481 u8 read[0x1];
482 u8 atomic[0x1];
483 u8 srq_receive[0x1];
484 u8 reserved_at_6[0x1a];
488 u8 reserved_at_0[0x60];
490 u8 ipv4[0x20];
494 u8 ipv6[16][0x8];
500 u8 reserved_at_0[0x80];
504 u8 smac_47_16[0x20];
506 u8 smac_15_0[0x10];
507 u8 ethertype[0x10];
509 u8 dmac_47_16[0x20];
511 u8 dmac_15_0[0x10];
512 u8 first_prio[0x3];
513 u8 first_cfi[0x1];
514 u8 first_vid[0xc];
516 u8 ip_protocol[0x8];
517 u8 ip_dscp[0x6];
518 u8 ip_ecn[0x2];
519 u8 cvlan_tag[0x1];
520 u8 svlan_tag[0x1];
521 u8 frag[0x1];
522 u8 ip_version[0x4];
523 u8 tcp_flags[0x9];
525 u8 tcp_sport[0x10];
526 u8 tcp_dport[0x10];
528 u8 reserved_at_c0[0x10];
529 u8 ipv4_ihl[0x4];
530 u8 reserved_at_c4[0x4];
532 u8 ttl_hoplimit[0x8];
534 u8 udp_sport[0x10];
535 u8 udp_dport[0x10];
543 u8 hi[0x18];
544 u8 lo[0x8];
549 u8 key[0x20];
553 u8 gre_c_present[0x1];
554 u8 reserved_at_1[0x1];
555 u8 gre_k_present[0x1];
556 u8 gre_s_present[0x1];
557 u8 source_vhca_port[0x4];
558 u8 source_sqn[0x18];
560 u8 source_eswitch_owner_vhca_id[0x10];
561 u8 source_port[0x10];
563 u8 outer_second_prio[0x3];
564 u8 outer_second_cfi[0x1];
565 u8 outer_second_vid[0xc];
566 u8 inner_second_prio[0x3];
567 u8 inner_second_cfi[0x1];
568 u8 inner_second_vid[0xc];
570 u8 outer_second_cvlan_tag[0x1];
571 u8 inner_second_cvlan_tag[0x1];
572 u8 outer_second_svlan_tag[0x1];
573 u8 inner_second_svlan_tag[0x1];
574 u8 reserved_at_64[0xc];
575 u8 gre_protocol[0x10];
579 u8 vxlan_vni[0x18];
580 u8 bth_opcode[0x8];
582 u8 geneve_vni[0x18];
583 u8 reserved_at_d8[0x6];
584 u8 geneve_tlv_option_0_exist[0x1];
585 u8 geneve_oam[0x1];
587 u8 reserved_at_e0[0xc];
588 u8 outer_ipv6_flow_label[0x14];
590 u8 reserved_at_100[0xc];
591 u8 inner_ipv6_flow_label[0x14];
593 u8 reserved_at_120[0xa];
594 u8 geneve_opt_len[0x6];
595 u8 geneve_protocol_type[0x10];
597 u8 reserved_at_140[0x8];
598 u8 bth_dst_qp[0x18];
599 u8 reserved_at_160[0x20];
600 u8 outer_esp_spi[0x20];
601 u8 reserved_at_1a0[0x60];
605 u8 mpls_label[0x14];
606 u8 mpls_exp[0x3];
607 u8 mpls_s_bos[0x1];
608 u8 mpls_ttl[0x8];
620 u8 metadata_reg_c_7[0x20];
622 u8 metadata_reg_c_6[0x20];
624 u8 metadata_reg_c_5[0x20];
626 u8 metadata_reg_c_4[0x20];
628 u8 metadata_reg_c_3[0x20];
630 u8 metadata_reg_c_2[0x20];
632 u8 metadata_reg_c_1[0x20];
634 u8 metadata_reg_c_0[0x20];
636 u8 metadata_reg_a[0x20];
638 u8 reserved_at_1a0[0x8];
640 u8 macsec_syndrome[0x8];
642 u8 reserved_at_1b0[0x50];
646 u8 inner_tcp_seq_num[0x20];
648 u8 outer_tcp_seq_num[0x20];
650 u8 inner_tcp_ack_num[0x20];
652 u8 outer_tcp_ack_num[0x20];
654 u8 reserved_at_80[0x8];
655 u8 outer_vxlan_gpe_vni[0x18];
657 u8 outer_vxlan_gpe_next_protocol[0x8];
658 u8 outer_vxlan_gpe_flags[0x8];
659 u8 reserved_at_b0[0x10];
661 u8 icmp_header_data[0x20];
663 u8 icmpv6_header_data[0x20];
665 u8 icmp_type[0x8];
666 u8 icmp_code[0x8];
667 u8 icmpv6_type[0x8];
668 u8 icmpv6_code[0x8];
670 u8 geneve_tlv_option_0_data[0x20];
672 u8 gtpu_teid[0x20];
674 u8 gtpu_msg_type[0x8];
675 u8 gtpu_msg_flags[0x8];
676 u8 reserved_at_170[0x10];
678 u8 gtpu_dw_2[0x20];
680 u8 gtpu_first_ext_dw_0[0x20];
682 u8 gtpu_dw_0[0x20];
684 u8 reserved_at_1e0[0x20];
688 u8 prog_sample_field_value_0[0x20];
690 u8 prog_sample_field_id_0[0x20];
692 u8 prog_sample_field_value_1[0x20];
694 u8 prog_sample_field_id_1[0x20];
696 u8 prog_sample_field_value_2[0x20];
698 u8 prog_sample_field_id_2[0x20];
700 u8 prog_sample_field_value_3[0x20];
702 u8 prog_sample_field_id_3[0x20];
704 u8 reserved_at_100[0x100];
708 u8 macsec_tag_0[0x20];
710 u8 macsec_tag_1[0x20];
712 u8 macsec_tag_2[0x20];
714 u8 macsec_tag_3[0x20];
716 u8 tunnel_header_0[0x20];
718 u8 tunnel_header_1[0x20];
720 u8 tunnel_header_2[0x20];
722 u8 tunnel_header_3[0x20];
724 u8 reserved_at_100[0x100];
728 u8 pa_h[0x20];
730 u8 pa_l[0x14];
731 u8 reserved_at_34[0xc];
735 u8 hi[0x20];
737 u8 lo[0x20];
741 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
742 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
743 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
744 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
745 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
746 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
747 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
748 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
749 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
750 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
754 u8 fl[0x1];
755 u8 free_ar[0x1];
756 u8 reserved_at_2[0xe];
757 u8 pkey_index[0x10];
759 u8 reserved_at_20[0x8];
760 u8 grh[0x1];
761 u8 mlid[0x7];
762 u8 rlid[0x10];
764 u8 ack_timeout[0x5];
765 u8 reserved_at_45[0x3];
766 u8 src_addr_index[0x8];
767 u8 reserved_at_50[0x4];
768 u8 stat_rate[0x4];
769 u8 hop_limit[0x8];
771 u8 reserved_at_60[0x4];
772 u8 tclass[0x8];
773 u8 flow_label[0x14];
775 u8 rgid_rip[16][0x8];
777 u8 reserved_at_100[0x4];
778 u8 f_dscp[0x1];
779 u8 f_ecn[0x1];
780 u8 reserved_at_106[0x1];
781 u8 f_eth_prio[0x1];
782 u8 ecn[0x2];
783 u8 dscp[0x6];
784 u8 udp_sport[0x10];
786 u8 dei_cfi[0x1];
787 u8 eth_prio[0x3];
788 u8 sl[0x4];
789 u8 vhca_port_num[0x8];
790 u8 rmac_47_32[0x10];
792 u8 rmac_31_0[0x20];
796 u8 nic_rx_multi_path_tirs[0x1];
797 u8 nic_rx_multi_path_tirs_fts[0x1];
798 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
799 u8 reserved_at_3[0x4];
800 u8 sw_owner_reformat_supported[0x1];
801 u8 reserved_at_8[0x18];
803 u8 encap_general_header[0x1];
804 u8 reserved_at_21[0xa];
805 u8 log_max_packet_reformat_context[0x5];
806 u8 reserved_at_30[0x6];
807 u8 max_encap_header_size[0xa];
808 u8 reserved_at_40[0x1c0];
822 u8 reserved_at_e00[0x700];
826 u8 reserved_at_1580[0x280];
830 u8 reserved_at_1880[0x780];
832 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
834 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
836 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
838 u8 reserved_at_20c0[0x5f40];
842 u8 reserved_at_0[0x10];
843 u8 port_select_flow_table[0x1];
844 u8 reserved_at_11[0x1];
845 u8 port_select_flow_table_bypass[0x1];
846 u8 reserved_at_13[0xd];
848 u8 reserved_at_20[0x1e0];
852 u8 reserved_at_400[0x7c00];
856 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
857 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
858 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
859 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
860 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
861 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
862 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
863 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
867 u8 fdb_to_vport_reg_c_id[0x8];
868 u8 reserved_at_8[0xd];
869 u8 fdb_modify_header_fwd_to_table[0x1];
870 u8 fdb_ipv4_ttl_modify[0x1];
871 u8 flow_source[0x1];
872 u8 reserved_at_18[0x2];
873 u8 multi_fdb_encap[0x1];
874 u8 egress_acl_forward_to_vport[0x1];
875 u8 fdb_multi_path_to_table[0x1];
876 u8 reserved_at_1d[0x3];
878 u8 reserved_at_20[0x1e0];
886 u8 reserved_at_800[0x1000];
888 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
890 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
892 u8 sw_steering_uplink_icm_address_rx[0x40];
894 u8 sw_steering_uplink_icm_address_tx[0x40];
896 u8 reserved_at_1900[0x6700];
900 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
901 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
905 u8 vport_svlan_strip[0x1];
906 u8 vport_cvlan_strip[0x1];
907 u8 vport_svlan_insert[0x1];
908 u8 vport_cvlan_insert_if_not_exist[0x1];
909 u8 vport_cvlan_insert_overwrite[0x1];
910 u8 reserved_at_5[0x2];
911 u8 esw_shared_ingress_acl[0x1];
912 u8 esw_uplink_ingress_acl[0x1];
913 u8 root_ft_on_other_esw[0x1];
914 u8 reserved_at_a[0xf];
915 u8 esw_functions_changed[0x1];
916 u8 reserved_at_1a[0x1];
917 u8 ecpf_vport_exists[0x1];
918 u8 counter_eswitch_affinity[0x1];
919 u8 merged_eswitch[0x1];
920 u8 nic_vport_node_guid_modify[0x1];
921 u8 nic_vport_port_guid_modify[0x1];
923 u8 vxlan_encap_decap[0x1];
924 u8 nvgre_encap_decap[0x1];
925 u8 reserved_at_22[0x1];
926 u8 log_max_fdb_encap_uplink[0x5];
927 u8 reserved_at_21[0x3];
928 u8 log_max_packet_reformat_context[0x5];
929 u8 reserved_2b[0x6];
930 u8 max_encap_header_size[0xa];
932 u8 reserved_at_40[0xb];
933 u8 log_max_esw_sf[0x5];
934 u8 esw_sf_base_id[0x10];
936 u8 reserved_at_60[0x7a0];
941 u8 packet_pacing[0x1];
942 u8 esw_scheduling[0x1];
943 u8 esw_bw_share[0x1];
944 u8 esw_rate_limit[0x1];
945 u8 reserved_at_4[0x1];
946 u8 packet_pacing_burst_bound[0x1];
947 u8 packet_pacing_typical_size[0x1];
948 u8 reserved_at_7[0x1];
949 u8 nic_sq_scheduling[0x1];
950 u8 nic_bw_share[0x1];
951 u8 nic_rate_limit[0x1];
952 u8 packet_pacing_uid[0x1];
953 u8 log_esw_max_sched_depth[0x4];
954 u8 reserved_at_10[0x10];
956 u8 reserved_at_20[0xb];
957 u8 log_max_qos_nic_queue_group[0x5];
958 u8 reserved_at_30[0x10];
960 u8 packet_pacing_max_rate[0x20];
962 u8 packet_pacing_min_rate[0x20];
964 u8 reserved_at_80[0x10];
965 u8 packet_pacing_rate_table_size[0x10];
967 u8 esw_element_type[0x10];
968 u8 esw_tsar_type[0x10];
970 u8 reserved_at_c0[0x10];
971 u8 max_qos_para_vport[0x10];
973 u8 max_tsar_bw_share[0x20];
975 u8 reserved_at_100[0x20];
977 u8 reserved_at_120[0x3];
978 u8 log_meter_aso_granularity[0x5];
979 u8 reserved_at_128[0x3];
980 u8 log_meter_aso_max_alloc[0x5];
981 u8 reserved_at_130[0x3];
982 u8 log_max_num_meter_aso[0x5];
983 u8 reserved_at_138[0x8];
985 u8 reserved_at_140[0x6c0];
989 u8 core_dump_general[0x1];
990 u8 core_dump_qp[0x1];
991 u8 reserved_at_2[0x7];
992 u8 resource_dump[0x1];
993 u8 reserved_at_a[0x16];
995 u8 reserved_at_20[0x2];
996 u8 stall_detect[0x1];
997 u8 reserved_at_23[0x1d];
999 u8 reserved_at_40[0x7c0];
1003 u8 csum_cap[0x1];
1004 u8 vlan_cap[0x1];
1005 u8 lro_cap[0x1];
1006 u8 lro_psh_flag[0x1];
1007 u8 lro_time_stamp[0x1];
1008 u8 reserved_at_5[0x2];
1009 u8 wqe_vlan_insert[0x1];
1010 u8 self_lb_en_modifiable[0x1];
1011 u8 reserved_at_9[0x2];
1012 u8 max_lso_cap[0x5];
1013 u8 multi_pkt_send_wqe[0x2];
1014 u8 wqe_inline_mode[0x2];
1015 u8 rss_ind_tbl_cap[0x4];
1016 u8 reg_umr_sq[0x1];
1017 u8 scatter_fcs[0x1];
1018 u8 enhanced_multi_pkt_send_wqe[0x1];
1019 u8 tunnel_lso_const_out_ip_id[0x1];
1020 u8 tunnel_lro_gre[0x1];
1021 u8 tunnel_lro_vxlan[0x1];
1022 u8 tunnel_stateless_gre[0x1];
1023 u8 tunnel_stateless_vxlan[0x1];
1025 u8 swp[0x1];
1026 u8 swp_csum[0x1];
1027 u8 swp_lso[0x1];
1028 u8 cqe_checksum_full[0x1];
1029 u8 tunnel_stateless_geneve_tx[0x1];
1030 u8 tunnel_stateless_mpls_over_udp[0x1];
1031 u8 tunnel_stateless_mpls_over_gre[0x1];
1032 u8 tunnel_stateless_vxlan_gpe[0x1];
1033 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
1034 u8 tunnel_stateless_ip_over_ip[0x1];
1035 u8 insert_trailer[0x1];
1036 u8 reserved_at_2b[0x1];
1037 u8 tunnel_stateless_ip_over_ip_rx[0x1];
1038 u8 tunnel_stateless_ip_over_ip_tx[0x1];
1039 u8 reserved_at_2e[0x2];
1040 u8 max_vxlan_udp_ports[0x8];
1041 u8 reserved_at_38[0x6];
1042 u8 max_geneve_opt_len[0x1];
1043 u8 tunnel_stateless_geneve_rx[0x1];
1045 u8 reserved_at_40[0x10];
1046 u8 lro_min_mss_size[0x10];
1048 u8 reserved_at_60[0x120];
1050 u8 lro_timer_supported_periods[4][0x20];
1052 u8 reserved_at_200[0x600];
1056 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1057 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1058 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1062 u8 roce_apm[0x1];
1063 u8 reserved_at_1[0x3];
1064 u8 sw_r_roce_src_udp_port[0x1];
1065 u8 fl_rc_qp_when_roce_disabled[0x1];
1066 u8 fl_rc_qp_when_roce_enabled[0x1];
1067 u8 reserved_at_7[0x17];
1068 u8 qp_ts_format[0x2];
1070 u8 reserved_at_20[0x60];
1072 u8 reserved_at_80[0xc];
1073 u8 l3_type[0x4];
1074 u8 reserved_at_90[0x8];
1075 u8 roce_version[0x8];
1077 u8 reserved_at_a0[0x10];
1078 u8 r_roce_dest_udp_port[0x10];
1080 u8 r_roce_max_src_udp_port[0x10];
1081 u8 r_roce_min_src_udp_port[0x10];
1083 u8 reserved_at_e0[0x10];
1084 u8 roce_address_table_size[0x10];
1086 u8 reserved_at_100[0x700];
1090 u8 opcode[0x10];
1091 u8 uid[0x10];
1093 u8 reserved_at_20[0x10];
1094 u8 op_mod[0x10];
1096 u8 reserved_at_40[0xc0];
1100 u8 status[0x8];
1101 u8 reserved_at_8[0x18];
1103 u8 syndrome[0x20];
1105 u8 reserved_at_40[0x40];
1109 u8 memic[0x1];
1110 u8 reserved_at_1[0x1f];
1112 u8 reserved_at_20[0xb];
1113 u8 log_min_memic_alloc_size[0x5];
1114 u8 reserved_at_30[0x8];
1115 u8 log_max_memic_addr_alignment[0x8];
1117 u8 memic_bar_start_addr[0x40];
1119 u8 memic_bar_size[0x20];
1121 u8 max_memic_size[0x20];
1123 u8 steering_sw_icm_start_address[0x40];
1125 u8 reserved_at_100[0x8];
1126 u8 log_header_modify_sw_icm_size[0x8];
1127 u8 reserved_at_110[0x2];
1128 u8 log_sw_icm_alloc_granularity[0x6];
1129 u8 log_steering_sw_icm_size[0x8];
1131 u8 reserved_at_120[0x18];
1132 u8 log_header_modify_pattern_sw_icm_size[0x8];
1134 u8 header_modify_sw_icm_start_address[0x40];
1136 u8 reserved_at_180[0x40];
1138 u8 header_modify_pattern_sw_icm_start_address[0x40];
1140 u8 memic_operations[0x20];
1142 u8 reserved_at_220[0x5e0];
1146 u8 user_affiliated_events[4][0x40];
1148 u8 user_unaffiliated_events[4][0x40];
1152 u8 desc_tunnel_offload_type[0x1];
1153 u8 eth_frame_offload_type[0x1];
1154 u8 virtio_version_1_0[0x1];
1155 u8 device_features_bits_mask[0xd];
1156 u8 event_mode[0x8];
1157 u8 virtio_queue_type[0x8];
1159 u8 max_tunnel_desc[0x10];
1160 u8 reserved_at_30[0x3];
1161 u8 log_doorbell_stride[0x5];
1162 u8 reserved_at_38[0x3];
1163 u8 log_doorbell_bar_size[0x5];
1165 u8 doorbell_bar_offset[0x40];
1167 u8 max_emulated_devices[0x8];
1168 u8 max_num_virtio_queues[0x18];
1170 u8 reserved_at_a0[0x60];
1172 u8 umem_1_buffer_param_a[0x20];
1174 u8 umem_1_buffer_param_b[0x20];
1176 u8 umem_2_buffer_param_a[0x20];
1178 u8 umem_2_buffer_param_b[0x20];
1180 u8 umem_3_buffer_param_a[0x20];
1182 u8 umem_3_buffer_param_b[0x20];
1184 u8 reserved_at_1c0[0x640];
1188 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1189 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1190 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1191 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1192 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1193 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1194 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1195 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1196 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1200 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1201 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1202 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1203 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1204 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1205 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1206 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1207 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1208 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1212 u8 reserved_at_0[0x40];
1214 u8 atomic_req_8B_endianness_mode[0x2];
1215 u8 reserved_at_42[0x4];
1216 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
1218 u8 reserved_at_47[0x19];
1220 u8 reserved_at_60[0x20];
1222 u8 reserved_at_80[0x10];
1223 u8 atomic_operations[0x10];
1225 u8 reserved_at_a0[0x10];
1226 u8 atomic_size_qp[0x10];
1228 u8 reserved_at_c0[0x10];
1229 u8 atomic_size_dc[0x10];
1231 u8 reserved_at_e0[0x720];
1235 u8 reserved_at_0[0x40];
1237 u8 sig[0x1];
1238 u8 reserved_at_41[0x1f];
1240 u8 reserved_at_60[0x20];
1252 u8 reserved_at_120[0x6E0];
1256 u8 reserved_at_0[0x10];
1257 u8 reserved_at_10[0x9];
1258 u8 op_swap_endianness[0x1];
1259 u8 op_min[0x1];
1260 u8 op_xor[0x1];
1261 u8 op_or[0x1];
1262 u8 op_and[0x1];
1263 u8 op_max[0x1];
1264 u8 op_add[0x1];
1268 u8 calc_matrix[0x1];
1269 u8 reserved_at_1[0x1f];
1270 u8 reserved_at_20[0x8];
1271 u8 max_vec_count[0x8];
1272 u8 reserved_at_30[0xd];
1273 u8 max_chunk_size[0x3];
1279 u8 reserved_at_c0[0x720];
1283 u8 tls_1_2_aes_gcm_128[0x1];
1284 u8 tls_1_3_aes_gcm_128[0x1];
1285 u8 tls_1_2_aes_gcm_256[0x1];
1286 u8 tls_1_3_aes_gcm_256[0x1];
1287 u8 reserved_at_4[0x1c];
1289 u8 reserved_at_20[0x7e0];
1293 u8 ipsec_full_offload[0x1];
1294 u8 ipsec_crypto_offload[0x1];
1295 u8 ipsec_esn[0x1];
1296 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1297 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1298 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1299 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1300 u8 reserved_at_7[0x4];
1301 u8 log_max_ipsec_offload[0x5];
1302 u8 reserved_at_10[0x10];
1304 u8 min_log_ipsec_full_replay_window[0x8];
1305 u8 max_log_ipsec_full_replay_window[0x8];
1306 u8 reserved_at_30[0x7d0];
1310 u8 macsec_epn[0x1];
1311 u8 reserved_at_1[0x2];
1312 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1313 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1314 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1315 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1316 u8 reserved_at_7[0x4];
1317 u8 log_max_macsec_offload[0x5];
1318 u8 reserved_at_10[0x10];
1320 u8 min_log_macsec_full_replay_window[0x8];
1321 u8 max_log_macsec_full_replay_window[0x8];
1322 u8 reserved_at_30[0x10];
1324 u8 reserved_at_40[0x7c0];
1328 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1329 MLX5_WQ_TYPE_CYCLIC = 0x1,
1330 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1331 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1335 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1336 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1340 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1341 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1342 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1343 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1344 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1348 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1349 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1350 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1351 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1352 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1353 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1357 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1358 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1362 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1363 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1364 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1368 MLX5_CAP_PORT_TYPE_IB = 0x0,
1369 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1373 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1374 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1375 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1394 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1401 MLX5_FC_BULK_128 = (1 << 0),
1416 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1422 u8 reserved_at_0[0x10];
1423 u8 shared_object_to_user_object_allowed[0x1];
1424 u8 reserved_at_13[0xe];
1425 u8 vhca_resource_manager[0x1];
1427 u8 hca_cap_2[0x1];
1428 u8 create_lag_when_not_master_up[0x1];
1429 u8 dtor[0x1];
1430 u8 event_on_vhca_state_teardown_request[0x1];
1431 u8 event_on_vhca_state_in_use[0x1];
1432 u8 event_on_vhca_state_active[0x1];
1433 u8 event_on_vhca_state_allocated[0x1];
1434 u8 event_on_vhca_state_invalid[0x1];
1435 u8 reserved_at_28[0x8];
1436 u8 vhca_id[0x10];
1438 u8 reserved_at_40[0x40];
1440 u8 log_max_srq_sz[0x8];
1441 u8 log_max_qp_sz[0x8];
1442 u8 event_cap[0x1];
1443 u8 reserved_at_91[0x2];
1444 u8 isolate_vl_tc_new[0x1];
1445 u8 reserved_at_94[0x4];
1446 u8 prio_tag_required[0x1];
1447 u8 reserved_at_99[0x2];
1448 u8 log_max_qp[0x5];
1450 u8 reserved_at_a0[0x3];
1451 u8 ece_support[0x1];
1452 u8 reserved_at_a4[0x5];
1453 u8 reg_c_preserve[0x1];
1454 u8 reserved_at_aa[0x1];
1455 u8 log_max_srq[0x5];
1456 u8 reserved_at_b0[0x1];
1457 u8 uplink_follow[0x1];
1458 u8 ts_cqe_to_dest_cqn[0x1];
1459 u8 reserved_at_b3[0x7];
1460 u8 shampo[0x1];
1461 u8 reserved_at_bb[0x5];
1463 u8 max_sgl_for_optimized_performance[0x8];
1464 u8 log_max_cq_sz[0x8];
1465 u8 relaxed_ordering_write_umr[0x1];
1466 u8 relaxed_ordering_read_umr[0x1];
1467 u8 reserved_at_d2[0x7];
1468 u8 virtio_net_device_emualtion_manager[0x1];
1469 u8 virtio_blk_device_emualtion_manager[0x1];
1470 u8 log_max_cq[0x5];
1472 u8 log_max_eq_sz[0x8];
1473 u8 relaxed_ordering_write[0x1];
1474 u8 relaxed_ordering_read[0x1];
1475 u8 log_max_mkey[0x6];
1476 u8 reserved_at_f0[0x8];
1477 u8 dump_fill_mkey[0x1];
1478 u8 reserved_at_f9[0x2];
1479 u8 fast_teardown[0x1];
1480 u8 log_max_eq[0x4];
1482 u8 max_indirection[0x8];
1483 u8 fixed_buffer_size[0x1];
1484 u8 log_max_mrw_sz[0x7];
1485 u8 force_teardown[0x1];
1486 u8 reserved_at_111[0x1];
1487 u8 log_max_bsf_list_size[0x6];
1488 u8 umr_extended_translation_offset[0x1];
1489 u8 null_mkey[0x1];
1490 u8 log_max_klm_list_size[0x6];
1492 u8 reserved_at_120[0xa];
1493 u8 log_max_ra_req_dc[0x6];
1494 u8 reserved_at_130[0x2];
1495 u8 eth_wqe_too_small[0x1];
1496 u8 reserved_at_133[0x6];
1497 u8 vnic_env_cq_overrun[0x1];
1498 u8 log_max_ra_res_dc[0x6];
1500 u8 reserved_at_140[0x5];
1501 u8 release_all_pages[0x1];
1502 u8 must_not_use[0x1];
1503 u8 reserved_at_147[0x2];
1504 u8 roce_accl[0x1];
1505 u8 log_max_ra_req_qp[0x6];
1506 u8 reserved_at_150[0xa];
1507 u8 log_max_ra_res_qp[0x6];
1509 u8 end_pad[0x1];
1510 u8 cc_query_allowed[0x1];
1511 u8 cc_modify_allowed[0x1];
1512 u8 start_pad[0x1];
1513 u8 cache_line_128byte[0x1];
1514 u8 reserved_at_165[0x4];
1515 u8 rts2rts_qp_counters_set_id[0x1];
1516 u8 reserved_at_16a[0x2];
1517 u8 vnic_env_int_rq_oob[0x1];
1518 u8 sbcam_reg[0x1];
1519 u8 reserved_at_16e[0x1];
1520 u8 qcam_reg[0x1];
1521 u8 gid_table_size[0x10];
1523 u8 out_of_seq_cnt[0x1];
1524 u8 vport_counters[0x1];
1525 u8 retransmission_q_counters[0x1];
1526 u8 debug[0x1];
1527 u8 modify_rq_counter_set_id[0x1];
1528 u8 rq_delay_drop[0x1];
1529 u8 max_qp_cnt[0xa];
1530 u8 pkey_table_size[0x10];
1532 u8 vport_group_manager[0x1];
1533 u8 vhca_group_manager[0x1];
1534 u8 ib_virt[0x1];
1535 u8 eth_virt[0x1];
1536 u8 vnic_env_queue_counters[0x1];
1537 u8 ets[0x1];
1538 u8 nic_flow_table[0x1];
1539 u8 eswitch_manager[0x1];
1540 u8 device_memory[0x1];
1541 u8 mcam_reg[0x1];
1542 u8 pcam_reg[0x1];
1543 u8 local_ca_ack_delay[0x5];
1544 u8 port_module_event[0x1];
1545 u8 enhanced_error_q_counters[0x1];
1546 u8 ports_check[0x1];
1547 u8 reserved_at_1b3[0x1];
1548 u8 disable_link_up[0x1];
1549 u8 beacon_led[0x1];
1550 u8 port_type[0x2];
1551 u8 num_ports[0x8];
1553 u8 reserved_at_1c0[0x1];
1554 u8 pps[0x1];
1555 u8 pps_modify[0x1];
1556 u8 log_max_msg[0x5];
1557 u8 reserved_at_1c8[0x4];
1558 u8 max_tc[0x4];
1559 u8 temp_warn_event[0x1];
1560 u8 dcbx[0x1];
1561 u8 general_notification_event[0x1];
1562 u8 reserved_at_1d3[0x2];
1563 u8 fpga[0x1];
1564 u8 rol_s[0x1];
1565 u8 rol_g[0x1];
1566 u8 reserved_at_1d8[0x1];
1567 u8 wol_s[0x1];
1568 u8 wol_g[0x1];
1569 u8 wol_a[0x1];
1570 u8 wol_b[0x1];
1571 u8 wol_m[0x1];
1572 u8 wol_u[0x1];
1573 u8 wol_p[0x1];
1575 u8 stat_rate_support[0x10];
1576 u8 reserved_at_1f0[0x1];
1577 u8 pci_sync_for_fw_update_event[0x1];
1578 u8 reserved_at_1f2[0x6];
1579 u8 init2_lag_tx_port_affinity[0x1];
1580 u8 reserved_at_1fa[0x3];
1581 u8 cqe_version[0x4];
1583 u8 compact_address_vector[0x1];
1584 u8 striding_rq[0x1];
1585 u8 reserved_at_202[0x1];
1586 u8 ipoib_enhanced_offloads[0x1];
1587 u8 ipoib_basic_offloads[0x1];
1588 u8 reserved_at_205[0x1];
1589 u8 repeated_block_disabled[0x1];
1590 u8 umr_modify_entity_size_disabled[0x1];
1591 u8 umr_modify_atomic_disabled[0x1];
1592 u8 umr_indirect_mkey_disabled[0x1];
1593 u8 umr_fence[0x2];
1594 u8 dc_req_scat_data_cqe[0x1];
1595 u8 reserved_at_20d[0x2];
1596 u8 drain_sigerr[0x1];
1597 u8 cmdif_checksum[0x2];
1598 u8 sigerr_cqe[0x1];
1599 u8 reserved_at_213[0x1];
1600 u8 wq_signature[0x1];
1601 u8 sctr_data_cqe[0x1];
1602 u8 reserved_at_216[0x1];
1603 u8 sho[0x1];
1604 u8 tph[0x1];
1605 u8 rf[0x1];
1606 u8 dct[0x1];
1607 u8 qos[0x1];
1608 u8 eth_net_offloads[0x1];
1609 u8 roce[0x1];
1610 u8 atomic[0x1];
1611 u8 reserved_at_21f[0x1];
1613 u8 cq_oi[0x1];
1614 u8 cq_resize[0x1];
1615 u8 cq_moderation[0x1];
1616 u8 reserved_at_223[0x3];
1617 u8 cq_eq_remap[0x1];
1618 u8 pg[0x1];
1619 u8 block_lb_mc[0x1];
1620 u8 reserved_at_229[0x1];
1621 u8 scqe_break_moderation[0x1];
1622 u8 cq_period_start_from_cqe[0x1];
1623 u8 cd[0x1];
1624 u8 reserved_at_22d[0x1];
1625 u8 apm[0x1];
1626 u8 vector_calc[0x1];
1627 u8 umr_ptr_rlky[0x1];
1628 u8 imaicl[0x1];
1629 u8 qp_packet_based[0x1];
1630 u8 reserved_at_233[0x3];
1631 u8 qkv[0x1];
1632 u8 pkv[0x1];
1633 u8 set_deth_sqpn[0x1];
1634 u8 reserved_at_239[0x3];
1635 u8 xrc[0x1];
1636 u8 ud[0x1];
1637 u8 uc[0x1];
1638 u8 rc[0x1];
1640 u8 uar_4k[0x1];
1641 u8 reserved_at_241[0x9];
1642 u8 uar_sz[0x6];
1643 u8 port_selection_cap[0x1];
1644 u8 reserved_at_248[0x1];
1645 u8 umem_uid_0[0x1];
1646 u8 reserved_at_250[0x5];
1647 u8 log_pg_sz[0x8];
1649 u8 bf[0x1];
1650 u8 driver_version[0x1];
1651 u8 pad_tx_eth_packet[0x1];
1652 u8 reserved_at_263[0x3];
1653 u8 mkey_by_name[0x1];
1654 u8 reserved_at_267[0x4];
1656 u8 log_bf_reg_size[0x5];
1658 u8 reserved_at_270[0x6];
1659 u8 lag_dct[0x2];
1660 u8 lag_tx_port_affinity[0x1];
1661 u8 lag_native_fdb_selection[0x1];
1662 u8 reserved_at_27a[0x1];
1663 u8 lag_master[0x1];
1664 u8 num_lag_ports[0x4];
1666 u8 reserved_at_280[0x10];
1667 u8 max_wqe_sz_sq[0x10];
1669 u8 reserved_at_2a0[0x10];
1670 u8 max_wqe_sz_rq[0x10];
1672 u8 max_flow_counter_31_16[0x10];
1673 u8 max_wqe_sz_sq_dc[0x10];
1675 u8 reserved_at_2e0[0x7];
1676 u8 max_qp_mcg[0x19];
1678 u8 reserved_at_300[0x10];
1679 u8 flow_counter_bulk_alloc[0x8];
1680 u8 log_max_mcg[0x8];
1682 u8 reserved_at_320[0x3];
1683 u8 log_max_transport_domain[0x5];
1684 u8 reserved_at_328[0x3];
1685 u8 log_max_pd[0x5];
1686 u8 reserved_at_330[0xb];
1687 u8 log_max_xrcd[0x5];
1689 u8 nic_receive_steering_discard[0x1];
1690 u8 receive_discard_vport_down[0x1];
1691 u8 transmit_discard_vport_down[0x1];
1692 u8 eq_overrun_count[0x1];
1693 u8 reserved_at_344[0x1];
1694 u8 invalid_command_count[0x1];
1695 u8 quota_exceeded_count[0x1];
1696 u8 reserved_at_347[0x1];
1697 u8 log_max_flow_counter_bulk[0x8];
1698 u8 max_flow_counter_15_0[0x10];
1701 u8 reserved_at_360[0x3];
1702 u8 log_max_rq[0x5];
1703 u8 reserved_at_368[0x3];
1704 u8 log_max_sq[0x5];
1705 u8 reserved_at_370[0x3];
1706 u8 log_max_tir[0x5];
1707 u8 reserved_at_378[0x3];
1708 u8 log_max_tis[0x5];
1710 u8 basic_cyclic_rcv_wqe[0x1];
1711 u8 reserved_at_381[0x2];
1712 u8 log_max_rmp[0x5];
1713 u8 reserved_at_388[0x3];
1714 u8 log_max_rqt[0x5];
1715 u8 reserved_at_390[0x3];
1716 u8 log_max_rqt_size[0x5];
1717 u8 reserved_at_398[0x3];
1718 u8 log_max_tis_per_sq[0x5];
1720 u8 ext_stride_num_range[0x1];
1721 u8 roce_rw_supported[0x1];
1722 u8 log_max_current_uc_list_wr_supported[0x1];
1723 u8 log_max_stride_sz_rq[0x5];
1724 u8 reserved_at_3a8[0x3];
1725 u8 log_min_stride_sz_rq[0x5];
1726 u8 reserved_at_3b0[0x3];
1727 u8 log_max_stride_sz_sq[0x5];
1728 u8 reserved_at_3b8[0x3];
1729 u8 log_min_stride_sz_sq[0x5];
1731 u8 hairpin[0x1];
1732 u8 reserved_at_3c1[0x2];
1733 u8 log_max_hairpin_queues[0x5];
1734 u8 reserved_at_3c8[0x3];
1735 u8 log_max_hairpin_wq_data_sz[0x5];
1736 u8 reserved_at_3d0[0x3];
1737 u8 log_max_hairpin_num_packets[0x5];
1738 u8 reserved_at_3d8[0x3];
1739 u8 log_max_wq_sz[0x5];
1741 u8 nic_vport_change_event[0x1];
1742 u8 disable_local_lb_uc[0x1];
1743 u8 disable_local_lb_mc[0x1];
1744 u8 log_min_hairpin_wq_data_sz[0x5];
1745 u8 reserved_at_3e8[0x2];
1746 u8 vhca_state[0x1];
1747 u8 log_max_vlan_list[0x5];
1748 u8 reserved_at_3f0[0x3];
1749 u8 log_max_current_mc_list[0x5];
1750 u8 reserved_at_3f8[0x3];
1751 u8 log_max_current_uc_list[0x5];
1753 u8 general_obj_types[0x40];
1755 u8 sq_ts_format[0x2];
1756 u8 rq_ts_format[0x2];
1757 u8 steering_format_version[0x4];
1758 u8 create_qp_start_hint[0x18];
1760 u8 reserved_at_460[0x1];
1761 u8 ats[0x1];
1762 u8 reserved_at_462[0x1];
1763 u8 log_max_uctx[0x5];
1764 u8 reserved_at_468[0x2];
1765 u8 ipsec_offload[0x1];
1766 u8 log_max_umem[0x5];
1767 u8 max_num_eqs[0x10];
1769 u8 reserved_at_480[0x1];
1770 u8 tls_tx[0x1];
1771 u8 tls_rx[0x1];
1772 u8 log_max_l2_table[0x5];
1773 u8 reserved_at_488[0x8];
1774 u8 log_uar_page_sz[0x10];
1776 u8 reserved_at_4a0[0x20];
1777 u8 device_frequency_mhz[0x20];
1778 u8 device_frequency_khz[0x20];
1780 u8 reserved_at_500[0x20];
1781 u8 num_of_uars_per_page[0x20];
1783 u8 flex_parser_protocols[0x20];
1785 u8 max_geneve_tlv_options[0x8];
1786 u8 reserved_at_568[0x3];
1787 u8 max_geneve_tlv_option_data_len[0x5];
1788 u8 reserved_at_570[0x9];
1789 u8 adv_virtualization[0x1];
1790 u8 reserved_at_57a[0x6];
1792 u8 reserved_at_580[0xb];
1793 u8 log_max_dci_stream_channels[0x5];
1794 u8 reserved_at_590[0x3];
1795 u8 log_max_dci_errored_streams[0x5];
1796 u8 reserved_at_598[0x8];
1798 u8 reserved_at_5a0[0x10];
1799 u8 enhanced_cqe_compression[0x1];
1800 u8 reserved_at_5b1[0x2];
1801 u8 log_max_dek[0x5];
1802 u8 reserved_at_5b8[0x4];
1803 u8 mini_cqe_resp_stride_index[0x1];
1804 u8 cqe_128_always[0x1];
1805 u8 cqe_compression_128[0x1];
1806 u8 cqe_compression[0x1];
1808 u8 cqe_compression_timeout[0x10];
1809 u8 cqe_compression_max_num[0x10];
1811 u8 reserved_at_5e0[0x8];
1812 u8 flex_parser_id_gtpu_dw_0[0x4];
1813 u8 reserved_at_5ec[0x4];
1814 u8 tag_matching[0x1];
1815 u8 rndv_offload_rc[0x1];
1816 u8 rndv_offload_dc[0x1];
1817 u8 log_tag_matching_list_sz[0x5];
1818 u8 reserved_at_5f8[0x3];
1819 u8 log_max_xrq[0x5];
1821 u8 affiliate_nic_vport_criteria[0x8];
1822 u8 native_port_num[0x8];
1823 u8 num_vhca_ports[0x8];
1824 u8 flex_parser_id_gtpu_teid[0x4];
1825 u8 reserved_at_61c[0x2];
1826 u8 sw_owner_id[0x1];
1827 u8 reserved_at_61f[0x1];
1829 u8 max_num_of_monitor_counters[0x10];
1830 u8 num_ppcnt_monitor_counters[0x10];
1832 u8 max_num_sf[0x10];
1833 u8 num_q_monitor_counters[0x10];
1835 u8 reserved_at_660[0x20];
1837 u8 sf[0x1];
1838 u8 sf_set_partition[0x1];
1839 u8 reserved_at_682[0x1];
1840 u8 log_max_sf[0x5];
1841 u8 apu[0x1];
1842 u8 reserved_at_689[0x4];
1843 u8 migration[0x1];
1844 u8 reserved_at_68e[0x2];
1845 u8 log_min_sf_size[0x8];
1846 u8 max_num_sf_partitions[0x8];
1848 u8 uctx_cap[0x20];
1850 u8 reserved_at_6c0[0x4];
1851 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1852 u8 flex_parser_id_icmp_dw1[0x4];
1853 u8 flex_parser_id_icmp_dw0[0x4];
1854 u8 flex_parser_id_icmpv6_dw1[0x4];
1855 u8 flex_parser_id_icmpv6_dw0[0x4];
1856 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1857 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1859 u8 max_num_match_definer[0x10];
1860 u8 sf_base_id[0x10];
1862 u8 flex_parser_id_gtpu_dw_2[0x4];
1863 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4];
1864 u8 num_total_dynamic_vf_msix[0x18];
1865 u8 reserved_at_720[0x14];
1866 u8 dynamic_msix_table_size[0xc];
1867 u8 reserved_at_740[0xc];
1868 u8 min_dynamic_vf_msix_table_size[0x4];
1869 u8 reserved_at_750[0x4];
1870 u8 max_dynamic_vf_msix_table_size[0xc];
1872 u8 reserved_at_760[0x20];
1873 u8 vhca_tunnel_commands[0x40];
1874 u8 match_definer_format_supported[0x40];
1878 u8 reserved_at_0[0xa0];
1880 u8 max_reformat_insert_size[0x8];
1881 u8 max_reformat_insert_offset[0x8];
1882 u8 max_reformat_remove_size[0x8];
1883 u8 max_reformat_remove_offset[0x8];
1885 u8 reserved_at_c0[0xe0];
1887 u8 reserved_at_1a0[0xb];
1888 u8 log_min_mkey_entity_size[0x5];
1889 u8 reserved_at_1b0[0x10];
1891 u8 reserved_at_1c0[0x60];
1893 u8 reserved_at_220[0x1];
1894 u8 sw_vhca_id_valid[0x1];
1895 u8 sw_vhca_id[0xe];
1896 u8 reserved_at_230[0x10];
1898 u8 reserved_at_240[0xb];
1899 u8 ts_cqe_metadata_size2wqe_counter[0x5];
1900 u8 reserved_at_250[0x10];
1902 u8 reserved_at_260[0x5a0];
1906 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1907 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1908 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2,
1909 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1910 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8,
1920 u8 destination_type[0x8];
1921 u8 destination_id[0x18];
1923 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1924 u8 packet_reformat[0x1];
1925 u8 reserved_at_22[0xe];
1926 u8 destination_eswitch_owner_vhca_id[0x10];
1930 u8 flow_counter_id[0x20];
1932 u8 reserved_at_20[0x20];
1938 u8 packet_reformat_id[0x20];
1940 u8 reserved_at_60[0x20];
1963 u8 reserved_at_e00[0x200];
1967 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1968 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1969 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1970 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1971 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1975 u8 l3_prot_type[0x1];
1976 u8 l4_prot_type[0x1];
1977 u8 selected_fields[0x1e];
1981 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1982 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1986 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1987 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1991 u8 wq_type[0x4];
1992 u8 wq_signature[0x1];
1993 u8 end_padding_mode[0x2];
1994 u8 cd_slave[0x1];
1995 u8 reserved_at_8[0x18];
1997 u8 hds_skip_first_sge[0x1];
1998 u8 log2_hds_buf_size[0x3];
1999 u8 reserved_at_24[0x7];
2000 u8 page_offset[0x5];
2001 u8 lwm[0x10];
2003 u8 reserved_at_40[0x8];
2004 u8 pd[0x18];
2006 u8 reserved_at_60[0x8];
2007 u8 uar_page[0x18];
2009 u8 dbr_addr[0x40];
2011 u8 hw_counter[0x20];
2013 u8 sw_counter[0x20];
2015 u8 reserved_at_100[0xc];
2016 u8 log_wq_stride[0x4];
2017 u8 reserved_at_110[0x3];
2018 u8 log_wq_pg_sz[0x5];
2019 u8 reserved_at_118[0x3];
2020 u8 log_wq_sz[0x5];
2022 u8 dbr_umem_valid[0x1];
2023 u8 wq_umem_valid[0x1];
2024 u8 reserved_at_122[0x1];
2025 u8 log_hairpin_num_packets[0x5];
2026 u8 reserved_at_128[0x3];
2027 u8 log_hairpin_data_sz[0x5];
2029 u8 reserved_at_130[0x4];
2030 u8 log_wqe_num_of_strides[0x4];
2031 u8 two_byte_shift_en[0x1];
2032 u8 reserved_at_139[0x4];
2033 u8 log_wqe_stride_size[0x3];
2035 u8 reserved_at_140[0x80];
2037 u8 headers_mkey[0x20];
2039 u8 shampo_enable[0x1];
2040 u8 reserved_at_1e1[0x4];
2041 u8 log_reservation_size[0x3];
2042 u8 reserved_at_1e8[0x5];
2043 u8 log_max_num_of_packets_per_reservation[0x3];
2044 u8 reserved_at_1f0[0x6];
2045 u8 log_headers_entry_size[0x2];
2046 u8 reserved_at_1f8[0x4];
2047 u8 log_headers_buffer_entry_num[0x4];
2049 u8 reserved_at_200[0x400];
2055 u8 reserved_at_0[0x8];
2056 u8 rq_num[0x18];
2060 u8 reserved_at_0[0x10];
2061 u8 mac_addr_47_32[0x10];
2063 u8 mac_addr_31_0[0x20];
2067 u8 reserved_at_0[0x14];
2068 u8 vlan[0x0c];
2070 u8 reserved_at_20[0x20];
2074 u8 reserved_at_0[0xa0];
2076 u8 min_time_between_cnps[0x20];
2078 u8 reserved_at_c0[0x12];
2079 u8 cnp_dscp[0x6];
2080 u8 reserved_at_d8[0x4];
2081 u8 cnp_prio_mode[0x1];
2082 u8 cnp_802p_prio[0x3];
2084 u8 reserved_at_e0[0x720];
2088 u8 reserved_at_0[0x60];
2090 u8 reserved_at_60[0x4];
2091 u8 clamp_tgt_rate[0x1];
2092 u8 reserved_at_65[0x3];
2093 u8 clamp_tgt_rate_after_time_inc[0x1];
2094 u8 reserved_at_69[0x17];
2096 u8 reserved_at_80[0x20];
2098 u8 rpg_time_reset[0x20];
2100 u8 rpg_byte_reset[0x20];
2102 u8 rpg_threshold[0x20];
2104 u8 rpg_max_rate[0x20];
2106 u8 rpg_ai_rate[0x20];
2108 u8 rpg_hai_rate[0x20];
2110 u8 rpg_gd[0x20];
2112 u8 rpg_min_dec_fac[0x20];
2114 u8 rpg_min_rate[0x20];
2116 u8 reserved_at_1c0[0xe0];
2118 u8 rate_to_set_on_first_cnp[0x20];
2120 u8 dce_tcp_g[0x20];
2122 u8 dce_tcp_rtt[0x20];
2124 u8 rate_reduce_monitor_period[0x20];
2126 u8 reserved_at_320[0x20];
2128 u8 initial_alpha_value[0x20];
2130 u8 reserved_at_360[0x4a0];
2134 u8 reserved_at_0[0x80];
2136 u8 rppp_max_rps[0x20];
2138 u8 rpg_time_reset[0x20];
2140 u8 rpg_byte_reset[0x20];
2142 u8 rpg_threshold[0x20];
2144 u8 rpg_max_rate[0x20];
2146 u8 rpg_ai_rate[0x20];
2148 u8 rpg_hai_rate[0x20];
2150 u8 rpg_gd[0x20];
2152 u8 rpg_min_dec_fac[0x20];
2154 u8 rpg_min_rate[0x20];
2156 u8 reserved_at_1c0[0x640];
2160 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
2161 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
2162 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
2166 u8 resize_field_select[0x20];
2170 u8 more_dump[0x1];
2171 u8 inline_dump[0x1];
2172 u8 reserved_at_2[0xa];
2173 u8 seq_num[0x4];
2174 u8 segment_type[0x10];
2176 u8 reserved_at_20[0x10];
2177 u8 vhca_id[0x10];
2179 u8 index1[0x20];
2181 u8 index2[0x20];
2183 u8 num_of_obj1[0x10];
2184 u8 num_of_obj2[0x10];
2186 u8 reserved_at_a0[0x20];
2188 u8 device_opaque[0x40];
2190 u8 mkey[0x20];
2192 u8 size[0x20];
2194 u8 address[0x40];
2196 u8 inline_data[52][0x20];
2200 u8 reserved_at_0[0x4];
2201 u8 num_of_obj2_supports_active[0x1];
2202 u8 num_of_obj2_supports_all[0x1];
2203 u8 must_have_num_of_obj2[0x1];
2204 u8 support_num_of_obj2[0x1];
2205 u8 num_of_obj1_supports_active[0x1];
2206 u8 num_of_obj1_supports_all[0x1];
2207 u8 must_have_num_of_obj1[0x1];
2208 u8 support_num_of_obj1[0x1];
2209 u8 must_have_index2[0x1];
2210 u8 support_index2[0x1];
2211 u8 must_have_index1[0x1];
2212 u8 support_index1[0x1];
2213 u8 segment_type[0x10];
2215 u8 segment_name[4][0x20];
2217 u8 index1_name[4][0x20];
2219 u8 index2_name[4][0x20];
2223 u8 length_dw[0x10];
2224 u8 segment_type[0x10];
2230 u8 segment_called[0x10];
2231 u8 vhca_id[0x10];
2233 u8 index1[0x20];
2235 u8 index2[0x20];
2237 u8 num_of_obj1[0x10];
2238 u8 num_of_obj2[0x10];
2244 u8 reserved_at_20[0x10];
2245 u8 syndrome_id[0x10];
2247 u8 reserved_at_40[0x40];
2249 u8 error[8][0x20];
2255 u8 reserved_at_20[0x18];
2256 u8 dump_version[0x8];
2258 u8 hw_version[0x20];
2260 u8 fw_version[0x20];
2266 u8 reserved_at_20[0x10];
2267 u8 num_of_records[0x10];
2275 u8 reserved_at_20[0x20];
2277 u8 index1[0x20];
2279 u8 index2[0x20];
2281 u8 payload[][0x20];
2296 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2297 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2298 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2299 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2303 u8 modify_field_select[0x20];
2307 u8 field_select_r_roce_np[0x20];
2311 u8 field_select_r_roce_rp[0x20];
2315 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2316 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2317 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2318 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2319 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2320 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2321 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2322 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2323 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2324 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2328 u8 field_select_8021qaurp[0x20];
2332 u8 time_since_last_clear_high[0x20];
2334 u8 time_since_last_clear_low[0x20];
2336 u8 symbol_errors_high[0x20];
2338 u8 symbol_errors_low[0x20];
2340 u8 sync_headers_errors_high[0x20];
2342 u8 sync_headers_errors_low[0x20];
2344 u8 edpl_bip_errors_lane0_high[0x20];
2346 u8 edpl_bip_errors_lane0_low[0x20];
2348 u8 edpl_bip_errors_lane1_high[0x20];
2350 u8 edpl_bip_errors_lane1_low[0x20];
2352 u8 edpl_bip_errors_lane2_high[0x20];
2354 u8 edpl_bip_errors_lane2_low[0x20];
2356 u8 edpl_bip_errors_lane3_high[0x20];
2358 u8 edpl_bip_errors_lane3_low[0x20];
2360 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2362 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2364 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2366 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2368 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2370 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2372 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2374 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2376 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2378 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2380 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2382 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2384 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2386 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2388 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2390 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2392 u8 rs_fec_corrected_blocks_high[0x20];
2394 u8 rs_fec_corrected_blocks_low[0x20];
2396 u8 rs_fec_uncorrectable_blocks_high[0x20];
2398 u8 rs_fec_uncorrectable_blocks_low[0x20];
2400 u8 rs_fec_no_errors_blocks_high[0x20];
2402 u8 rs_fec_no_errors_blocks_low[0x20];
2404 u8 rs_fec_single_error_blocks_high[0x20];
2406 u8 rs_fec_single_error_blocks_low[0x20];
2408 u8 rs_fec_corrected_symbols_total_high[0x20];
2410 u8 rs_fec_corrected_symbols_total_low[0x20];
2412 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2414 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2416 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2418 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2420 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2422 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2424 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2426 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2428 u8 link_down_events[0x20];
2430 u8 successful_recovery_events[0x20];
2432 u8 reserved_at_640[0x180];
2436 u8 time_since_last_clear_high[0x20];
2438 u8 time_since_last_clear_low[0x20];
2440 u8 phy_received_bits_high[0x20];
2442 u8 phy_received_bits_low[0x20];
2444 u8 phy_symbol_errors_high[0x20];
2446 u8 phy_symbol_errors_low[0x20];
2448 u8 phy_corrected_bits_high[0x20];
2450 u8 phy_corrected_bits_low[0x20];
2452 u8 phy_corrected_bits_lane0_high[0x20];
2454 u8 phy_corrected_bits_lane0_low[0x20];
2456 u8 phy_corrected_bits_lane1_high[0x20];
2458 u8 phy_corrected_bits_lane1_low[0x20];
2460 u8 phy_corrected_bits_lane2_high[0x20];
2462 u8 phy_corrected_bits_lane2_low[0x20];
2464 u8 phy_corrected_bits_lane3_high[0x20];
2466 u8 phy_corrected_bits_lane3_low[0x20];
2468 u8 reserved_at_200[0x5c0];
2472 u8 symbol_error_counter[0x10];
2474 u8 link_error_recovery_counter[0x8];
2476 u8 link_downed_counter[0x8];
2478 u8 port_rcv_errors[0x10];
2480 u8 port_rcv_remote_physical_errors[0x10];
2482 u8 port_rcv_switch_relay_errors[0x10];
2484 u8 port_xmit_discards[0x10];
2486 u8 port_xmit_constraint_errors[0x8];
2488 u8 port_rcv_constraint_errors[0x8];
2490 u8 reserved_at_70[0x8];
2492 u8 link_overrun_errors[0x8];
2494 u8 reserved_at_80[0x10];
2496 u8 vl_15_dropped[0x10];
2498 u8 reserved_at_a0[0x80];
2500 u8 port_xmit_wait[0x20];
2504 u8 transmit_queue_high[0x20];
2506 u8 transmit_queue_low[0x20];
2508 u8 no_buffer_discard_uc_high[0x20];
2510 u8 no_buffer_discard_uc_low[0x20];
2512 u8 reserved_at_80[0x740];
2516 u8 wred_discard_high[0x20];
2518 u8 wred_discard_low[0x20];
2520 u8 ecn_marked_tc_high[0x20];
2522 u8 ecn_marked_tc_low[0x20];
2524 u8 reserved_at_80[0x740];
2528 u8 rx_octets_high[0x20];
2530 u8 rx_octets_low[0x20];
2532 u8 reserved_at_40[0xc0];
2534 u8 rx_frames_high[0x20];
2536 u8 rx_frames_low[0x20];
2538 u8 tx_octets_high[0x20];
2540 u8 tx_octets_low[0x20];
2542 u8 reserved_at_180[0xc0];
2544 u8 tx_frames_high[0x20];
2546 u8 tx_frames_low[0x20];
2548 u8 rx_pause_high[0x20];
2550 u8 rx_pause_low[0x20];
2552 u8 rx_pause_duration_high[0x20];
2554 u8 rx_pause_duration_low[0x20];
2556 u8 tx_pause_high[0x20];
2558 u8 tx_pause_low[0x20];
2560 u8 tx_pause_duration_high[0x20];
2562 u8 tx_pause_duration_low[0x20];
2564 u8 rx_pause_transition_high[0x20];
2566 u8 rx_pause_transition_low[0x20];
2568 u8 rx_discards_high[0x20];
2570 u8 rx_discards_low[0x20];
2572 u8 device_stall_minor_watermark_cnt_high[0x20];
2574 u8 device_stall_minor_watermark_cnt_low[0x20];
2576 u8 device_stall_critical_watermark_cnt_high[0x20];
2578 u8 device_stall_critical_watermark_cnt_low[0x20];
2580 u8 reserved_at_480[0x340];
2584 u8 port_transmit_wait_high[0x20];
2586 u8 port_transmit_wait_low[0x20];
2588 u8 reserved_at_40[0x100];
2590 u8 rx_buffer_almost_full_high[0x20];
2592 u8 rx_buffer_almost_full_low[0x20];
2594 u8 rx_buffer_full_high[0x20];
2596 u8 rx_buffer_full_low[0x20];
2598 u8 rx_icrc_encapsulated_high[0x20];
2600 u8 rx_icrc_encapsulated_low[0x20];
2602 u8 reserved_at_200[0x5c0];
2606 u8 dot3stats_alignment_errors_high[0x20];
2608 u8 dot3stats_alignment_errors_low[0x20];
2610 u8 dot3stats_fcs_errors_high[0x20];
2612 u8 dot3stats_fcs_errors_low[0x20];
2614 u8 dot3stats_single_collision_frames_high[0x20];
2616 u8 dot3stats_single_collision_frames_low[0x20];
2618 u8 dot3stats_multiple_collision_frames_high[0x20];
2620 u8 dot3stats_multiple_collision_frames_low[0x20];
2622 u8 dot3stats_sqe_test_errors_high[0x20];
2624 u8 dot3stats_sqe_test_errors_low[0x20];
2626 u8 dot3stats_deferred_transmissions_high[0x20];
2628 u8 dot3stats_deferred_transmissions_low[0x20];
2630 u8 dot3stats_late_collisions_high[0x20];
2632 u8 dot3stats_late_collisions_low[0x20];
2634 u8 dot3stats_excessive_collisions_high[0x20];
2636 u8 dot3stats_excessive_collisions_low[0x20];
2638 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2640 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2642 u8 dot3stats_carrier_sense_errors_high[0x20];
2644 u8 dot3stats_carrier_sense_errors_low[0x20];
2646 u8 dot3stats_frame_too_longs_high[0x20];
2648 u8 dot3stats_frame_too_longs_low[0x20];
2650 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2652 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2654 u8 dot3stats_symbol_errors_high[0x20];
2656 u8 dot3stats_symbol_errors_low[0x20];
2658 u8 dot3control_in_unknown_opcodes_high[0x20];
2660 u8 dot3control_in_unknown_opcodes_low[0x20];
2662 u8 dot3in_pause_frames_high[0x20];
2664 u8 dot3in_pause_frames_low[0x20];
2666 u8 dot3out_pause_frames_high[0x20];
2668 u8 dot3out_pause_frames_low[0x20];
2670 u8 reserved_at_400[0x3c0];
2674 u8 ether_stats_drop_events_high[0x20];
2676 u8 ether_stats_drop_events_low[0x20];
2678 u8 ether_stats_octets_high[0x20];
2680 u8 ether_stats_octets_low[0x20];
2682 u8 ether_stats_pkts_high[0x20];
2684 u8 ether_stats_pkts_low[0x20];
2686 u8 ether_stats_broadcast_pkts_high[0x20];
2688 u8 ether_stats_broadcast_pkts_low[0x20];
2690 u8 ether_stats_multicast_pkts_high[0x20];
2692 u8 ether_stats_multicast_pkts_low[0x20];
2694 u8 ether_stats_crc_align_errors_high[0x20];
2696 u8 ether_stats_crc_align_errors_low[0x20];
2698 u8 ether_stats_undersize_pkts_high[0x20];
2700 u8 ether_stats_undersize_pkts_low[0x20];
2702 u8 ether_stats_oversize_pkts_high[0x20];
2704 u8 ether_stats_oversize_pkts_low[0x20];
2706 u8 ether_stats_fragments_high[0x20];
2708 u8 ether_stats_fragments_low[0x20];
2710 u8 ether_stats_jabbers_high[0x20];
2712 u8 ether_stats_jabbers_low[0x20];
2714 u8 ether_stats_collisions_high[0x20];
2716 u8 ether_stats_collisions_low[0x20];
2718 u8 ether_stats_pkts64octets_high[0x20];
2720 u8 ether_stats_pkts64octets_low[0x20];
2722 u8 ether_stats_pkts65to127octets_high[0x20];
2724 u8 ether_stats_pkts65to127octets_low[0x20];
2726 u8 ether_stats_pkts128to255octets_high[0x20];
2728 u8 ether_stats_pkts128to255octets_low[0x20];
2730 u8 ether_stats_pkts256to511octets_high[0x20];
2732 u8 ether_stats_pkts256to511octets_low[0x20];
2734 u8 ether_stats_pkts512to1023octets_high[0x20];
2736 u8 ether_stats_pkts512to1023octets_low[0x20];
2738 u8 ether_stats_pkts1024to1518octets_high[0x20];
2740 u8 ether_stats_pkts1024to1518octets_low[0x20];
2742 u8 ether_stats_pkts1519to2047octets_high[0x20];
2744 u8 ether_stats_pkts1519to2047octets_low[0x20];
2746 u8 ether_stats_pkts2048to4095octets_high[0x20];
2748 u8 ether_stats_pkts2048to4095octets_low[0x20];
2750 u8 ether_stats_pkts4096to8191octets_high[0x20];
2752 u8 ether_stats_pkts4096to8191octets_low[0x20];
2754 u8 ether_stats_pkts8192to10239octets_high[0x20];
2756 u8 ether_stats_pkts8192to10239octets_low[0x20];
2758 u8 reserved_at_540[0x280];
2762 u8 if_in_octets_high[0x20];
2764 u8 if_in_octets_low[0x20];
2766 u8 if_in_ucast_pkts_high[0x20];
2768 u8 if_in_ucast_pkts_low[0x20];
2770 u8 if_in_discards_high[0x20];
2772 u8 if_in_discards_low[0x20];
2774 u8 if_in_errors_high[0x20];
2776 u8 if_in_errors_low[0x20];
2778 u8 if_in_unknown_protos_high[0x20];
2780 u8 if_in_unknown_protos_low[0x20];
2782 u8 if_out_octets_high[0x20];
2784 u8 if_out_octets_low[0x20];
2786 u8 if_out_ucast_pkts_high[0x20];
2788 u8 if_out_ucast_pkts_low[0x20];
2790 u8 if_out_discards_high[0x20];
2792 u8 if_out_discards_low[0x20];
2794 u8 if_out_errors_high[0x20];
2796 u8 if_out_errors_low[0x20];
2798 u8 if_in_multicast_pkts_high[0x20];
2800 u8 if_in_multicast_pkts_low[0x20];
2802 u8 if_in_broadcast_pkts_high[0x20];
2804 u8 if_in_broadcast_pkts_low[0x20];
2806 u8 if_out_multicast_pkts_high[0x20];
2808 u8 if_out_multicast_pkts_low[0x20];
2810 u8 if_out_broadcast_pkts_high[0x20];
2812 u8 if_out_broadcast_pkts_low[0x20];
2814 u8 reserved_at_340[0x480];
2818 u8 a_frames_transmitted_ok_high[0x20];
2820 u8 a_frames_transmitted_ok_low[0x20];
2822 u8 a_frames_received_ok_high[0x20];
2824 u8 a_frames_received_ok_low[0x20];
2826 u8 a_frame_check_sequence_errors_high[0x20];
2828 u8 a_frame_check_sequence_errors_low[0x20];
2830 u8 a_alignment_errors_high[0x20];
2832 u8 a_alignment_errors_low[0x20];
2834 u8 a_octets_transmitted_ok_high[0x20];
2836 u8 a_octets_transmitted_ok_low[0x20];
2838 u8 a_octets_received_ok_high[0x20];
2840 u8 a_octets_received_ok_low[0x20];
2842 u8 a_multicast_frames_xmitted_ok_high[0x20];
2844 u8 a_multicast_frames_xmitted_ok_low[0x20];
2846 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2848 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2850 u8 a_multicast_frames_received_ok_high[0x20];
2852 u8 a_multicast_frames_received_ok_low[0x20];
2854 u8 a_broadcast_frames_received_ok_high[0x20];
2856 u8 a_broadcast_frames_received_ok_low[0x20];
2858 u8 a_in_range_length_errors_high[0x20];
2860 u8 a_in_range_length_errors_low[0x20];
2862 u8 a_out_of_range_length_field_high[0x20];
2864 u8 a_out_of_range_length_field_low[0x20];
2866 u8 a_frame_too_long_errors_high[0x20];
2868 u8 a_frame_too_long_errors_low[0x20];
2870 u8 a_symbol_error_during_carrier_high[0x20];
2872 u8 a_symbol_error_during_carrier_low[0x20];
2874 u8 a_mac_control_frames_transmitted_high[0x20];
2876 u8 a_mac_control_frames_transmitted_low[0x20];
2878 u8 a_mac_control_frames_received_high[0x20];
2880 u8 a_mac_control_frames_received_low[0x20];
2882 u8 a_unsupported_opcodes_received_high[0x20];
2884 u8 a_unsupported_opcodes_received_low[0x20];
2886 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2888 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2890 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2892 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2894 u8 reserved_at_4c0[0x300];
2898 u8 life_time_counter_high[0x20];
2900 u8 life_time_counter_low[0x20];
2902 u8 rx_errors[0x20];
2904 u8 tx_errors[0x20];
2906 u8 l0_to_recovery_eieos[0x20];
2908 u8 l0_to_recovery_ts[0x20];
2910 u8 l0_to_recovery_framing[0x20];
2912 u8 l0_to_recovery_retrain[0x20];
2914 u8 crc_error_dllp[0x20];
2916 u8 crc_error_tlp[0x20];
2918 u8 tx_overflow_buffer_pkt_high[0x20];
2920 u8 tx_overflow_buffer_pkt_low[0x20];
2922 u8 outbound_stalled_reads[0x20];
2924 u8 outbound_stalled_writes[0x20];
2926 u8 outbound_stalled_reads_events[0x20];
2928 u8 outbound_stalled_writes_events[0x20];
2930 u8 reserved_at_200[0x5c0];
2934 u8 command_completion_vector[0x20];
2936 u8 reserved_at_20[0xc0];
2940 u8 reserved_at_0[0x18];
2941 u8 port_num[0x1];
2942 u8 reserved_at_19[0x3];
2943 u8 vl[0x4];
2945 u8 reserved_at_20[0xa0];
2949 u8 event_subtype[0x8];
2950 u8 reserved_at_8[0x8];
2951 u8 congestion_level[0x8];
2952 u8 reserved_at_18[0x8];
2954 u8 reserved_at_20[0xa0];
2958 u8 reserved_at_0[0x60];
2960 u8 gpio_event_hi[0x20];
2962 u8 gpio_event_lo[0x20];
2964 u8 reserved_at_a0[0x40];
2968 u8 reserved_at_0[0x40];
2970 u8 port_num[0x4];
2971 u8 reserved_at_44[0x1c];
2973 u8 reserved_at_60[0x80];
2977 u8 reserved_at_0[0xe0];
2981 u8 to_multiplier[0x3];
2982 u8 reserved_at_3[0x9];
2983 u8 to_value[0x14];
2987 u8 reserved_at_0[0x20];
2991 u8 reserved_at_40[0x60];
3011 u8 reserved_at_1c0[0x40];
3015 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
3016 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
3020 u8 reserved_at_0[0x8];
3021 u8 cqn[0x18];
3023 u8 reserved_at_20[0x20];
3025 u8 reserved_at_40[0x18];
3026 u8 syndrome[0x8];
3028 u8 reserved_at_60[0x80];
3032 u8 bytes_committed[0x20];
3034 u8 r_key[0x20];
3036 u8 reserved_at_40[0x10];
3037 u8 packet_len[0x10];
3039 u8 rdma_op_len[0x20];
3041 u8 rdma_va[0x40];
3043 u8 reserved_at_c0[0x5];
3044 u8 rdma[0x1];
3045 u8 write[0x1];
3046 u8 requestor[0x1];
3047 u8 qp_number[0x18];
3051 u8 bytes_committed[0x20];
3053 u8 reserved_at_20[0x10];
3054 u8 wqe_index[0x10];
3056 u8 reserved_at_40[0x10];
3057 u8 len[0x10];
3059 u8 reserved_at_60[0x60];
3061 u8 reserved_at_c0[0x5];
3062 u8 rdma[0x1];
3063 u8 write_read[0x1];
3064 u8 requestor[0x1];
3065 u8 qpn[0x18];
3069 u8 reserved_at_0[0xa0];
3071 u8 type[0x8];
3072 u8 reserved_at_a8[0x18];
3074 u8 reserved_at_c0[0x8];
3075 u8 qpn_rqn_sqn[0x18];
3079 u8 reserved_at_0[0xc0];
3081 u8 reserved_at_c0[0x8];
3082 u8 dct_number[0x18];
3086 u8 reserved_at_0[0xc0];
3088 u8 reserved_at_c0[0x8];
3089 u8 cq_number[0x18];
3093 MLX5_QPC_STATE_RST = 0x0,
3094 MLX5_QPC_STATE_INIT = 0x1,
3095 MLX5_QPC_STATE_RTR = 0x2,
3096 MLX5_QPC_STATE_RTS = 0x3,
3097 MLX5_QPC_STATE_SQER = 0x4,
3098 MLX5_QPC_STATE_ERR = 0x6,
3099 MLX5_QPC_STATE_SQD = 0x7,
3100 MLX5_QPC_STATE_SUSPENDED = 0x9,
3104 MLX5_QPC_ST_RC = 0x0,
3105 MLX5_QPC_ST_UC = 0x1,
3106 MLX5_QPC_ST_UD = 0x2,
3107 MLX5_QPC_ST_XRC = 0x3,
3108 MLX5_QPC_ST_DCI = 0x5,
3109 MLX5_QPC_ST_QP0 = 0x7,
3110 MLX5_QPC_ST_QP1 = 0x8,
3111 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
3112 MLX5_QPC_ST_REG_UMR = 0xc,
3116 MLX5_QPC_PM_STATE_ARMED = 0x0,
3117 MLX5_QPC_PM_STATE_REARM = 0x1,
3118 MLX5_QPC_PM_STATE_RESERVED = 0x2,
3119 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
3123 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
3127 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
3128 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
3132 MLX5_QPC_MTU_256_BYTES = 0x1,
3133 MLX5_QPC_MTU_512_BYTES = 0x2,
3134 MLX5_QPC_MTU_1K_BYTES = 0x3,
3135 MLX5_QPC_MTU_2K_BYTES = 0x4,
3136 MLX5_QPC_MTU_4K_BYTES = 0x5,
3137 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
3141 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
3142 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
3143 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
3144 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
3145 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
3146 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
3147 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
3148 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
3152 MLX5_QPC_CS_REQ_DISABLE = 0x0,
3153 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
3154 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
3158 MLX5_QPC_CS_RES_DISABLE = 0x0,
3159 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
3160 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
3164 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3165 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1,
3166 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
3170 u8 state[0x4];
3171 u8 lag_tx_port_affinity[0x4];
3172 u8 st[0x8];
3173 u8 reserved_at_10[0x2];
3174 u8 isolate_vl_tc[0x1];
3175 u8 pm_state[0x2];
3176 u8 reserved_at_15[0x1];
3177 u8 req_e2e_credit_mode[0x2];
3178 u8 offload_type[0x4];
3179 u8 end_padding_mode[0x2];
3180 u8 reserved_at_1e[0x2];
3182 u8 wq_signature[0x1];
3183 u8 block_lb_mc[0x1];
3184 u8 atomic_like_write_en[0x1];
3185 u8 latency_sensitive[0x1];
3186 u8 reserved_at_24[0x1];
3187 u8 drain_sigerr[0x1];
3188 u8 reserved_at_26[0x2];
3189 u8 pd[0x18];
3191 u8 mtu[0x3];
3192 u8 log_msg_max[0x5];
3193 u8 reserved_at_48[0x1];
3194 u8 log_rq_size[0x4];
3195 u8 log_rq_stride[0x3];
3196 u8 no_sq[0x1];
3197 u8 log_sq_size[0x4];
3198 u8 reserved_at_55[0x3];
3199 u8 ts_format[0x2];
3200 u8 reserved_at_5a[0x1];
3201 u8 rlky[0x1];
3202 u8 ulp_stateless_offload_mode[0x4];
3204 u8 counter_set_id[0x8];
3205 u8 uar_page[0x18];
3207 u8 reserved_at_80[0x8];
3208 u8 user_index[0x18];
3210 u8 reserved_at_a0[0x3];
3211 u8 log_page_size[0x5];
3212 u8 remote_qpn[0x18];
3218 u8 log_ack_req_freq[0x4];
3219 u8 reserved_at_384[0x4];
3220 u8 log_sra_max[0x3];
3221 u8 reserved_at_38b[0x2];
3222 u8 retry_count[0x3];
3223 u8 rnr_retry[0x3];
3224 u8 reserved_at_393[0x1];
3225 u8 fre[0x1];
3226 u8 cur_rnr_retry[0x3];
3227 u8 cur_retry_count[0x3];
3228 u8 reserved_at_39b[0x5];
3230 u8 reserved_at_3a0[0x20];
3232 u8 reserved_at_3c0[0x8];
3233 u8 next_send_psn[0x18];
3235 u8 reserved_at_3e0[0x3];
3236 u8 log_num_dci_stream_channels[0x5];
3237 u8 cqn_snd[0x18];
3239 u8 reserved_at_400[0x3];
3240 u8 log_num_dci_errored_streams[0x5];
3241 u8 deth_sqpn[0x18];
3243 u8 reserved_at_420[0x20];
3245 u8 reserved_at_440[0x8];
3246 u8 last_acked_psn[0x18];
3248 u8 reserved_at_460[0x8];
3249 u8 ssn[0x18];
3251 u8 reserved_at_480[0x8];
3252 u8 log_rra_max[0x3];
3253 u8 reserved_at_48b[0x1];
3254 u8 atomic_mode[0x4];
3255 u8 rre[0x1];
3256 u8 rwe[0x1];
3257 u8 rae[0x1];
3258 u8 reserved_at_493[0x1];
3259 u8 page_offset[0x6];
3260 u8 reserved_at_49a[0x3];
3261 u8 cd_slave_receive[0x1];
3262 u8 cd_slave_send[0x1];
3263 u8 cd_master[0x1];
3265 u8 reserved_at_4a0[0x3];
3266 u8 min_rnr_nak[0x5];
3267 u8 next_rcv_psn[0x18];
3269 u8 reserved_at_4c0[0x8];
3270 u8 xrcd[0x18];
3272 u8 reserved_at_4e0[0x8];
3273 u8 cqn_rcv[0x18];
3275 u8 dbr_addr[0x40];
3277 u8 q_key[0x20];
3279 u8 reserved_at_560[0x5];
3280 u8 rq_type[0x3];
3281 u8 srqn_rmpn_xrqn[0x18];
3283 u8 reserved_at_580[0x8];
3284 u8 rmsn[0x18];
3286 u8 hw_sq_wqebb_counter[0x10];
3287 u8 sw_sq_wqebb_counter[0x10];
3289 u8 hw_rq_counter[0x20];
3291 u8 sw_rq_counter[0x20];
3293 u8 reserved_at_600[0x20];
3295 u8 reserved_at_620[0xf];
3296 u8 cgs[0x1];
3297 u8 cs_req[0x8];
3298 u8 cs_res[0x8];
3300 u8 dc_access_key[0x40];
3302 u8 reserved_at_680[0x3];
3303 u8 dbr_umem_valid[0x1];
3305 u8 reserved_at_684[0xbc];
3309 u8 source_l3_address[16][0x8];
3311 u8 reserved_at_80[0x3];
3312 u8 vlan_valid[0x1];
3313 u8 vlan_id[0xc];
3314 u8 source_mac_47_32[0x10];
3316 u8 source_mac_31_0[0x20];
3318 u8 reserved_at_c0[0x14];
3319 u8 roce_l3_type[0x4];
3320 u8 roce_version[0x8];
3322 u8 reserved_at_e0[0x20];
3326 u8 reserved_at_0[0x3];
3327 u8 shampo_log_max_reservation_size[0x5];
3328 u8 reserved_at_8[0x3];
3329 u8 shampo_log_min_reservation_size[0x5];
3330 u8 shampo_min_mss_size[0x10];
3332 u8 reserved_at_20[0x3];
3333 u8 shampo_max_log_headers_entry_size[0x5];
3334 u8 reserved_at_28[0x18];
3336 u8 reserved_at_40[0x7c0];
3359 u8 reserved_at_0[0x8000];
3363 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3364 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3365 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
3366 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
3367 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3368 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
3369 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
3370 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3371 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3372 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3373 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3374 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3375 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3376 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3380 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3381 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3382 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3386 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0,
3387 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1,
3391 u8 ethtype[0x10];
3392 u8 prio[0x3];
3393 u8 cfi[0x1];
3394 u8 vid[0xc];
3398 MLX5_FLOW_METER_COLOR_RED = 0x0,
3399 MLX5_FLOW_METER_COLOR_YELLOW = 0x1,
3400 MLX5_FLOW_METER_COLOR_GREEN = 0x2,
3401 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
3405 MLX5_EXE_ASO_FLOW_METER = 0x2,
3409 u8 return_reg_id[0x4];
3410 u8 aso_type[0x4];
3411 u8 reserved_at_8[0x14];
3412 u8 action[0x1];
3413 u8 init_color[0x2];
3414 u8 meter_id[0x1];
3422 u8 valid[0x1];
3423 u8 reserved_at_1[0x7];
3424 u8 aso_object_id[0x18];
3432 u8 group_id[0x20];
3434 u8 reserved_at_40[0x8];
3435 u8 flow_tag[0x18];
3437 u8 reserved_at_60[0x10];
3438 u8 action[0x10];
3440 u8 extended_destination[0x1];
3441 u8 reserved_at_81[0x1];
3442 u8 flow_source[0x2];
3443 u8 encrypt_decrypt_type[0x4];
3444 u8 destination_list_size[0x18];
3446 u8 reserved_at_a0[0x8];
3447 u8 flow_counter_list_size[0x18];
3449 u8 packet_reformat_id[0x20];
3451 u8 modify_header_id[0x20];
3455 u8 encrypt_decrypt_obj_id[0x20];
3456 u8 reserved_at_140[0xc0];
3462 u8 reserved_at_1300[0x500];
3468 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3469 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3473 u8 state[0x4];
3474 u8 log_xrc_srq_size[0x4];
3475 u8 reserved_at_8[0x18];
3477 u8 wq_signature[0x1];
3478 u8 cont_srq[0x1];
3479 u8 reserved_at_22[0x1];
3480 u8 rlky[0x1];
3481 u8 basic_cyclic_rcv_wqe[0x1];
3482 u8 log_rq_stride[0x3];
3483 u8 xrcd[0x18];
3485 u8 page_offset[0x6];
3486 u8 reserved_at_46[0x1];
3487 u8 dbr_umem_valid[0x1];
3488 u8 cqn[0x18];
3490 u8 reserved_at_60[0x20];
3492 u8 user_index_equal_xrc_srqn[0x1];
3493 u8 reserved_at_81[0x1];
3494 u8 log_page_size[0x6];
3495 u8 user_index[0x18];
3497 u8 reserved_at_a0[0x20];
3499 u8 reserved_at_c0[0x8];
3500 u8 pd[0x18];
3502 u8 lwm[0x10];
3503 u8 wqe_cnt[0x10];
3505 u8 reserved_at_100[0x40];
3507 u8 db_record_addr_h[0x20];
3509 u8 db_record_addr_l[0x1e];
3510 u8 reserved_at_17e[0x2];
3512 u8 reserved_at_180[0x80];
3516 u8 counter_error_queues[0x20];
3518 u8 total_error_queues[0x20];
3520 u8 send_queue_priority_update_flow[0x20];
3522 u8 reserved_at_60[0x20];
3524 u8 nic_receive_steering_discard[0x40];
3526 u8 receive_discard_vport_down[0x40];
3528 u8 transmit_discard_vport_down[0x40];
3530 u8 async_eq_overrun[0x20];
3532 u8 comp_eq_overrun[0x20];
3534 u8 reserved_at_180[0x20];
3536 u8 invalid_command[0x20];
3538 u8 quota_exceeded_command[0x20];
3540 u8 internal_rq_out_of_buffer[0x20];
3542 u8 cq_overrun[0x20];
3544 u8 eth_wqe_too_small[0x20];
3546 u8 reserved_at_220[0xdc0];
3550 u8 packets[0x40];
3552 u8 octets[0x40];
3556 u8 strict_lag_tx_port_affinity[0x1];
3557 u8 tls_en[0x1];
3558 u8 reserved_at_2[0x2];
3559 u8 lag_tx_port_affinity[0x04];
3561 u8 reserved_at_8[0x4];
3562 u8 prio[0x4];
3563 u8 reserved_at_10[0x10];
3565 u8 reserved_at_20[0x100];
3567 u8 reserved_at_120[0x8];
3568 u8 transport_domain[0x18];
3570 u8 reserved_at_140[0x8];
3571 u8 underlay_qpn[0x18];
3573 u8 reserved_at_160[0x8];
3574 u8 pd[0x18];
3576 u8 reserved_at_180[0x380];
3580 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3581 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3585 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0),
3590 MLX5_RX_HASH_FN_NONE = 0x0,
3591 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3592 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
3596 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3597 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
3601 u8 reserved_at_0[0x20];
3603 u8 disp_type[0x4];
3604 u8 tls_en[0x1];
3605 u8 reserved_at_25[0x1b];
3607 u8 reserved_at_40[0x40];
3609 u8 reserved_at_80[0x4];
3610 u8 lro_timeout_period_usecs[0x10];
3611 u8 packet_merge_mask[0x4];
3612 u8 lro_max_ip_payload_size[0x8];
3614 u8 reserved_at_a0[0x40];
3616 u8 reserved_at_e0[0x8];
3617 u8 inline_rqn[0x18];
3619 u8 rx_hash_symmetric[0x1];
3620 u8 reserved_at_101[0x1];
3621 u8 tunneled_offload_en[0x1];
3622 u8 reserved_at_103[0x5];
3623 u8 indirect_table[0x18];
3625 u8 rx_hash_fn[0x4];
3626 u8 reserved_at_124[0x2];
3627 u8 self_lb_block[0x2];
3628 u8 transport_domain[0x18];
3630 u8 rx_hash_toeplitz_key[10][0x20];
3636 u8 reserved_at_2c0[0x4c0];
3640 MLX5_SRQC_STATE_GOOD = 0x0,
3641 MLX5_SRQC_STATE_ERROR = 0x1,
3645 u8 state[0x4];
3646 u8 log_srq_size[0x4];
3647 u8 reserved_at_8[0x18];
3649 u8 wq_signature[0x1];
3650 u8 cont_srq[0x1];
3651 u8 reserved_at_22[0x1];
3652 u8 rlky[0x1];
3653 u8 reserved_at_24[0x1];
3654 u8 log_rq_stride[0x3];
3655 u8 xrcd[0x18];
3657 u8 page_offset[0x6];
3658 u8 reserved_at_46[0x2];
3659 u8 cqn[0x18];
3661 u8 reserved_at_60[0x20];
3663 u8 reserved_at_80[0x2];
3664 u8 log_page_size[0x6];
3665 u8 reserved_at_88[0x18];
3667 u8 reserved_at_a0[0x20];
3669 u8 reserved_at_c0[0x8];
3670 u8 pd[0x18];
3672 u8 lwm[0x10];
3673 u8 wqe_cnt[0x10];
3675 u8 reserved_at_100[0x40];
3677 u8 dbr_addr[0x40];
3679 u8 reserved_at_180[0x80];
3683 MLX5_SQC_STATE_RST = 0x0,
3684 MLX5_SQC_STATE_RDY = 0x1,
3685 MLX5_SQC_STATE_ERR = 0x3,
3689 u8 rlky[0x1];
3690 u8 cd_master[0x1];
3691 u8 fre[0x1];
3692 u8 flush_in_error_en[0x1];
3693 u8 allow_multi_pkt_send_wqe[0x1];
3694 u8 min_wqe_inline_mode[0x3];
3695 u8 state[0x4];
3696 u8 reg_umr[0x1];
3697 u8 allow_swp[0x1];
3698 u8 hairpin[0x1];
3699 u8 reserved_at_f[0xb];
3700 u8 ts_format[0x2];
3701 u8 reserved_at_1c[0x4];
3703 u8 reserved_at_20[0x8];
3704 u8 user_index[0x18];
3706 u8 reserved_at_40[0x8];
3707 u8 cqn[0x18];
3709 u8 reserved_at_60[0x8];
3710 u8 hairpin_peer_rq[0x18];
3712 u8 reserved_at_80[0x10];
3713 u8 hairpin_peer_vhca[0x10];
3715 u8 reserved_at_a0[0x20];
3717 u8 reserved_at_c0[0x8];
3718 u8 ts_cqe_to_dest_cqn[0x18];
3720 u8 reserved_at_e0[0x10];
3721 u8 packet_pacing_rate_limit_index[0x10];
3722 u8 tis_lst_sz[0x10];
3723 u8 qos_queue_group_id[0x10];
3725 u8 reserved_at_120[0x40];
3727 u8 reserved_at_160[0x8];
3728 u8 tis_num_0[0x18];
3734 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3735 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3736 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3737 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3738 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3742 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3749 u8 element_type[0x8];
3750 u8 reserved_at_8[0x18];
3752 u8 element_attributes[0x20];
3754 u8 parent_element_id[0x20];
3756 u8 reserved_at_60[0x40];
3758 u8 bw_share[0x20];
3760 u8 max_average_bw[0x20];
3762 u8 reserved_at_e0[0x120];
3766 u8 reserved_at_0[0xa0];
3768 u8 reserved_at_a0[0x5];
3769 u8 list_q_type[0x3];
3770 u8 reserved_at_a8[0x8];
3771 u8 rqt_max_size[0x10];
3773 u8 rq_vhca_id_format[0x1];
3774 u8 reserved_at_c1[0xf];
3775 u8 rqt_actual_size[0x10];
3777 u8 reserved_at_e0[0x6a0];
3783 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3784 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3788 MLX5_RQC_STATE_RST = 0x0,
3789 MLX5_RQC_STATE_RDY = 0x1,
3790 MLX5_RQC_STATE_ERR = 0x3,
3794 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0,
3795 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1,
3796 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2,
3800 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0,
3801 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1,
3802 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2,
3806 u8 rlky[0x1];
3807 u8 delay_drop_en[0x1];
3808 u8 scatter_fcs[0x1];
3809 u8 vsd[0x1];
3810 u8 mem_rq_type[0x4];
3811 u8 state[0x4];
3812 u8 reserved_at_c[0x1];
3813 u8 flush_in_error_en[0x1];
3814 u8 hairpin[0x1];
3815 u8 reserved_at_f[0xb];
3816 u8 ts_format[0x2];
3817 u8 reserved_at_1c[0x4];
3819 u8 reserved_at_20[0x8];
3820 u8 user_index[0x18];
3822 u8 reserved_at_40[0x8];
3823 u8 cqn[0x18];
3825 u8 counter_set_id[0x8];
3826 u8 reserved_at_68[0x18];
3828 u8 reserved_at_80[0x8];
3829 u8 rmpn[0x18];
3831 u8 reserved_at_a0[0x8];
3832 u8 hairpin_peer_sq[0x18];
3834 u8 reserved_at_c0[0x10];
3835 u8 hairpin_peer_vhca[0x10];
3837 u8 reserved_at_e0[0x46];
3838 u8 shampo_no_match_alignment_granularity[0x2];
3839 u8 reserved_at_128[0x6];
3840 u8 shampo_match_criteria_type[0x2];
3841 u8 reservation_timeout[0x10];
3843 u8 reserved_at_140[0x40];
3849 MLX5_RMPC_STATE_RDY = 0x1,
3850 MLX5_RMPC_STATE_ERR = 0x3,
3854 u8 reserved_at_0[0x8];
3855 u8 state[0x4];
3856 u8 reserved_at_c[0x14];
3858 u8 basic_cyclic_rcv_wqe[0x1];
3859 u8 reserved_at_21[0x1f];
3861 u8 reserved_at_40[0x140];
3867 VHCA_ID_TYPE_HW = 0,
3872 u8 reserved_at_0[0x5];
3873 u8 min_wqe_inline_mode[0x3];
3874 u8 reserved_at_8[0x15];
3875 u8 disable_mc_local_lb[0x1];
3876 u8 disable_uc_local_lb[0x1];
3877 u8 roce_en[0x1];
3879 u8 arm_change_event[0x1];
3880 u8 reserved_at_21[0x1a];
3881 u8 event_on_mtu[0x1];
3882 u8 event_on_promisc_change[0x1];
3883 u8 event_on_vlan_change[0x1];
3884 u8 event_on_mc_address_change[0x1];
3885 u8 event_on_uc_address_change[0x1];
3887 u8 vhca_id_type[0x1];
3888 u8 reserved_at_41[0xb];
3889 u8 affiliation_criteria[0x4];
3890 u8 affiliated_vhca_id[0x10];
3892 u8 reserved_at_60[0xd0];
3894 u8 mtu[0x10];
3896 u8 system_image_guid[0x40];
3897 u8 port_guid[0x40];
3898 u8 node_guid[0x40];
3900 u8 reserved_at_200[0x140];
3901 u8 qkey_violation_counter[0x10];
3902 u8 reserved_at_350[0x430];
3904 u8 promisc_uc[0x1];
3905 u8 promisc_mc[0x1];
3906 u8 promisc_all[0x1];
3907 u8 reserved_at_783[0x2];
3908 u8 allowed_list_type[0x3];
3909 u8 reserved_at_788[0xc];
3910 u8 allowed_list_size[0xc];
3914 u8 reserved_at_7e0[0x20];
3916 u8 current_uc_mac_address[][0x40];
3920 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3921 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3922 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3923 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3924 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3925 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3929 u8 reserved_at_0[0x1];
3930 u8 free[0x1];
3931 u8 reserved_at_2[0x1];
3932 u8 access_mode_4_2[0x3];
3933 u8 reserved_at_6[0x7];
3934 u8 relaxed_ordering_write[0x1];
3935 u8 reserved_at_e[0x1];
3936 u8 small_fence_on_rdma_read_response[0x1];
3937 u8 umr_en[0x1];
3938 u8 a[0x1];
3939 u8 rw[0x1];
3940 u8 rr[0x1];
3941 u8 lw[0x1];
3942 u8 lr[0x1];
3943 u8 access_mode_1_0[0x2];
3944 u8 reserved_at_18[0x2];
3945 u8 ma_translation_mode[0x2];
3946 u8 reserved_at_1c[0x4];
3948 u8 qpn[0x18];
3949 u8 mkey_7_0[0x8];
3951 u8 reserved_at_40[0x20];
3953 u8 length64[0x1];
3954 u8 bsf_en[0x1];
3955 u8 sync_umr[0x1];
3956 u8 reserved_at_63[0x2];
3957 u8 expected_sigerr_count[0x1];
3958 u8 reserved_at_66[0x1];
3959 u8 en_rinval[0x1];
3960 u8 pd[0x18];
3962 u8 start_addr[0x40];
3964 u8 len[0x40];
3966 u8 bsf_octword_size[0x20];
3968 u8 reserved_at_120[0x80];
3970 u8 translations_octword_size[0x20];
3972 u8 reserved_at_1c0[0x19];
3973 u8 relaxed_ordering_read[0x1];
3974 u8 reserved_at_1d9[0x1];
3975 u8 log_page_size[0x5];
3977 u8 reserved_at_1e0[0x20];
3981 u8 reserved_at_0[0x10];
3982 u8 pkey[0x10];
3986 u8 array128_auto[16][0x8];
3990 u8 field_select[0x20];
3992 u8 reserved_at_20[0xe0];
3994 u8 sm_virt_aware[0x1];
3995 u8 has_smi[0x1];
3996 u8 has_raw[0x1];
3997 u8 grh_required[0x1];
3998 u8 reserved_at_104[0xc];
3999 u8 port_physical_state[0x4];
4000 u8 vport_state_policy[0x4];
4001 u8 port_state[0x4];
4002 u8 vport_state[0x4];
4004 u8 reserved_at_120[0x20];
4006 u8 system_image_guid[0x40];
4008 u8 port_guid[0x40];
4010 u8 node_guid[0x40];
4012 u8 cap_mask1[0x20];
4014 u8 cap_mask1_field_select[0x20];
4016 u8 cap_mask2[0x20];
4018 u8 cap_mask2_field_select[0x20];
4020 u8 reserved_at_280[0x80];
4022 u8 lid[0x10];
4023 u8 reserved_at_310[0x4];
4024 u8 init_type_reply[0x4];
4025 u8 lmc[0x3];
4026 u8 subnet_timeout[0x5];
4028 u8 sm_lid[0x10];
4029 u8 sm_sl[0x4];
4030 u8 reserved_at_334[0xc];
4032 u8 qkey_violation_counter[0x10];
4033 u8 pkey_violation_counter[0x10];
4035 u8 reserved_at_360[0xca0];
4039 u8 fdb_to_vport_reg_c[0x1];
4040 u8 reserved_at_1[0x2];
4041 u8 vport_svlan_strip[0x1];
4042 u8 vport_cvlan_strip[0x1];
4043 u8 vport_svlan_insert[0x1];
4044 u8 vport_cvlan_insert[0x2];
4045 u8 fdb_to_vport_reg_c_id[0x8];
4046 u8 reserved_at_10[0x10];
4048 u8 reserved_at_20[0x20];
4050 u8 svlan_cfi[0x1];
4051 u8 svlan_pcp[0x3];
4052 u8 svlan_id[0xc];
4053 u8 cvlan_cfi[0x1];
4054 u8 cvlan_pcp[0x3];
4055 u8 cvlan_id[0xc];
4057 u8 reserved_at_60[0x720];
4059 u8 sw_steering_vport_icm_address_rx[0x40];
4061 u8 sw_steering_vport_icm_address_tx[0x40];
4065 MLX5_EQC_STATUS_OK = 0x0,
4066 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
4070 MLX5_EQC_ST_ARMED = 0x9,
4071 MLX5_EQC_ST_FIRED = 0xa,
4075 u8 status[0x4];
4076 u8 reserved_at_4[0x9];
4077 u8 ec[0x1];
4078 u8 oi[0x1];
4079 u8 reserved_at_f[0x5];
4080 u8 st[0x4];
4081 u8 reserved_at_18[0x8];
4083 u8 reserved_at_20[0x20];
4085 u8 reserved_at_40[0x14];
4086 u8 page_offset[0x6];
4087 u8 reserved_at_5a[0x6];
4089 u8 reserved_at_60[0x3];
4090 u8 log_eq_size[0x5];
4091 u8 uar_page[0x18];
4093 u8 reserved_at_80[0x20];
4095 u8 reserved_at_a0[0x14];
4096 u8 intr[0xc];
4098 u8 reserved_at_c0[0x3];
4099 u8 log_page_size[0x5];
4100 u8 reserved_at_c8[0x18];
4102 u8 reserved_at_e0[0x60];
4104 u8 reserved_at_140[0x8];
4105 u8 consumer_counter[0x18];
4107 u8 reserved_at_160[0x8];
4108 u8 producer_counter[0x18];
4110 u8 reserved_at_180[0x80];
4114 MLX5_DCTC_STATE_ACTIVE = 0x0,
4115 MLX5_DCTC_STATE_DRAINING = 0x1,
4116 MLX5_DCTC_STATE_DRAINED = 0x2,
4120 MLX5_DCTC_CS_RES_DISABLE = 0x0,
4121 MLX5_DCTC_CS_RES_NA = 0x1,
4122 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
4126 MLX5_DCTC_MTU_256_BYTES = 0x1,
4127 MLX5_DCTC_MTU_512_BYTES = 0x2,
4128 MLX5_DCTC_MTU_1K_BYTES = 0x3,
4129 MLX5_DCTC_MTU_2K_BYTES = 0x4,
4130 MLX5_DCTC_MTU_4K_BYTES = 0x5,
4134 u8 reserved_at_0[0x4];
4135 u8 state[0x4];
4136 u8 reserved_at_8[0x18];
4138 u8 reserved_at_20[0x8];
4139 u8 user_index[0x18];
4141 u8 reserved_at_40[0x8];
4142 u8 cqn[0x18];
4144 u8 counter_set_id[0x8];
4145 u8 atomic_mode[0x4];
4146 u8 rre[0x1];
4147 u8 rwe[0x1];
4148 u8 rae[0x1];
4149 u8 atomic_like_write_en[0x1];
4150 u8 latency_sensitive[0x1];
4151 u8 rlky[0x1];
4152 u8 free_ar[0x1];
4153 u8 reserved_at_73[0xd];
4155 u8 reserved_at_80[0x8];
4156 u8 cs_res[0x8];
4157 u8 reserved_at_90[0x3];
4158 u8 min_rnr_nak[0x5];
4159 u8 reserved_at_98[0x8];
4161 u8 reserved_at_a0[0x8];
4162 u8 srqn_xrqn[0x18];
4164 u8 reserved_at_c0[0x8];
4165 u8 pd[0x18];
4167 u8 tclass[0x8];
4168 u8 reserved_at_e8[0x4];
4169 u8 flow_label[0x14];
4171 u8 dc_access_key[0x40];
4173 u8 reserved_at_140[0x5];
4174 u8 mtu[0x3];
4175 u8 port[0x8];
4176 u8 pkey_index[0x10];
4178 u8 reserved_at_160[0x8];
4179 u8 my_addr_index[0x8];
4180 u8 reserved_at_170[0x8];
4181 u8 hop_limit[0x8];
4183 u8 dc_access_key_violation_count[0x20];
4185 u8 reserved_at_1a0[0x14];
4186 u8 dei_cfi[0x1];
4187 u8 eth_prio[0x3];
4188 u8 ecn[0x2];
4189 u8 dscp[0x6];
4191 u8 reserved_at_1c0[0x20];
4192 u8 ece[0x20];
4196 MLX5_CQC_STATUS_OK = 0x0,
4197 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
4198 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
4202 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
4203 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
4207 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
4208 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
4209 MLX5_CQC_ST_FIRED = 0xa,
4213 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4214 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4219 u8 status[0x4];
4220 u8 reserved_at_4[0x2];
4221 u8 dbr_umem_valid[0x1];
4222 u8 apu_cq[0x1];
4223 u8 cqe_sz[0x3];
4224 u8 cc[0x1];
4225 u8 reserved_at_c[0x1];
4226 u8 scqe_break_moderation_en[0x1];
4227 u8 oi[0x1];
4228 u8 cq_period_mode[0x2];
4229 u8 cqe_comp_en[0x1];
4230 u8 mini_cqe_res_format[0x2];
4231 u8 st[0x4];
4232 u8 reserved_at_18[0x6];
4233 u8 cqe_compression_layout[0x2];
4235 u8 reserved_at_20[0x20];
4237 u8 reserved_at_40[0x14];
4238 u8 page_offset[0x6];
4239 u8 reserved_at_5a[0x6];
4241 u8 reserved_at_60[0x3];
4242 u8 log_cq_size[0x5];
4243 u8 uar_page[0x18];
4245 u8 reserved_at_80[0x4];
4246 u8 cq_period[0xc];
4247 u8 cq_max_count[0x10];
4249 u8 c_eqn_or_apu_element[0x20];
4251 u8 reserved_at_c0[0x3];
4252 u8 log_page_size[0x5];
4253 u8 reserved_at_c8[0x18];
4255 u8 reserved_at_e0[0x20];
4257 u8 reserved_at_100[0x8];
4258 u8 last_notified_index[0x18];
4260 u8 reserved_at_120[0x8];
4261 u8 last_solicit_index[0x18];
4263 u8 reserved_at_140[0x8];
4264 u8 consumer_counter[0x18];
4266 u8 reserved_at_160[0x8];
4267 u8 producer_counter[0x18];
4269 u8 reserved_at_180[0x40];
4271 u8 dbr_addr[0x40];
4278 u8 reserved_at_0[0x800];
4282 u8 reserved_at_0[0xc0];
4284 u8 reserved_at_c0[0x8];
4285 u8 ieee_vendor_id[0x18];
4287 u8 reserved_at_e0[0x10];
4288 u8 vsd_vendor_id[0x10];
4290 u8 vsd[208][0x8];
4292 u8 vsd_contd_psid[16][0x8];
4296 MLX5_XRQC_STATE_GOOD = 0x0,
4297 MLX5_XRQC_STATE_ERROR = 0x1,
4301 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4302 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
4306 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4310 u8 log_matching_list_sz[0x4];
4311 u8 reserved_at_4[0xc];
4312 u8 append_next_index[0x10];
4314 u8 sw_phase_cnt[0x10];
4315 u8 hw_phase_cnt[0x10];
4317 u8 reserved_at_40[0x40];
4321 u8 state[0x4];
4322 u8 rlkey[0x1];
4323 u8 reserved_at_5[0xf];
4324 u8 topology[0x4];
4325 u8 reserved_at_18[0x4];
4326 u8 offload[0x4];
4328 u8 reserved_at_20[0x8];
4329 u8 user_index[0x18];
4331 u8 reserved_at_40[0x8];
4332 u8 cqn[0x18];
4334 u8 reserved_at_60[0xa0];
4338 u8 reserved_at_180[0x280];
4346 u8 reserved_at_0[0x20];
4353 u8 reserved_at_0[0x20];
4368 u8 reserved_at_0[0x7c0];
4373 u8 reserved_at_0[0x7c0];
4389 u8 reserved_at_0[0xe0];
4393 u8 reserved_at_0[0x100];
4395 u8 assert_existptr[0x20];
4397 u8 assert_callra[0x20];
4399 u8 reserved_at_140[0x20];
4401 u8 time[0x20];
4403 u8 fw_version[0x20];
4405 u8 hw_id[0x20];
4407 u8 rfr[0x1];
4408 u8 reserved_at_1c1[0x3];
4409 u8 valid[0x1];
4410 u8 severity[0x3];
4411 u8 reserved_at_1c8[0x18];
4413 u8 irisc_index[0x8];
4414 u8 synd[0x8];
4415 u8 ext_synd[0x10];
4419 u8 no_lb[0x1];
4420 u8 reserved_at_1[0x7];
4421 u8 port[0x8];
4422 u8 reserved_at_10[0x10];
4424 u8 reserved_at_20[0x60];
4428 u8 traffic_class[0x4];
4429 u8 reserved_at_4[0xc];
4430 u8 vport_number[0x10];
4434 u8 reserved_at_0[0x10];
4435 u8 vport_number[0x10];
4439 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4440 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4441 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4445 u8 reserved_at_0[0x8];
4446 u8 tsar_type[0x8];
4447 u8 reserved_at_10[0x10];
4451 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4452 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4456 u8 status[0x8];
4457 u8 reserved_at_8[0x18];
4459 u8 syndrome[0x20];
4461 u8 reserved_at_40[0x3f];
4463 u8 state[0x1];
4467 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
4468 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
4469 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4473 u8 opcode[0x10];
4474 u8 reserved_at_10[0x10];
4476 u8 reserved_at_20[0x10];
4477 u8 op_mod[0x10];
4479 u8 reserved_at_40[0x10];
4480 u8 profile[0x10];
4482 u8 reserved_at_60[0x20];
4486 u8 status[0x8];
4487 u8 reserved_at_8[0x18];
4489 u8 syndrome[0x20];
4491 u8 reserved_at_40[0x40];
4495 u8 opcode[0x10];
4496 u8 uid[0x10];
4498 u8 reserved_at_20[0x10];
4499 u8 op_mod[0x10];
4501 u8 reserved_at_40[0x8];
4502 u8 qpn[0x18];
4504 u8 reserved_at_60[0x20];
4506 u8 opt_param_mask[0x20];
4508 u8 reserved_at_a0[0x20];
4512 u8 reserved_at_800[0x80];
4516 u8 status[0x8];
4517 u8 reserved_at_8[0x18];
4519 u8 syndrome[0x20];
4521 u8 reserved_at_40[0x40];
4525 u8 opcode[0x10];
4526 u8 uid[0x10];
4528 u8 reserved_at_20[0x10];
4529 u8 op_mod[0x10];
4531 u8 reserved_at_40[0x8];
4532 u8 qpn[0x18];
4534 u8 reserved_at_60[0x20];
4536 u8 opt_param_mask[0x20];
4538 u8 reserved_at_a0[0x20];
4542 u8 reserved_at_800[0x80];
4546 u8 status[0x8];
4547 u8 reserved_at_8[0x18];
4549 u8 syndrome[0x20];
4551 u8 reserved_at_40[0x40];
4555 u8 opcode[0x10];
4556 u8 reserved_at_10[0x10];
4558 u8 reserved_at_20[0x10];
4559 u8 op_mod[0x10];
4561 u8 roce_address_index[0x10];
4562 u8 reserved_at_50[0xc];
4563 u8 vhca_port_num[0x4];
4565 u8 reserved_at_60[0x20];
4571 u8 status[0x8];
4572 u8 reserved_at_8[0x18];
4574 u8 syndrome[0x20];
4576 u8 reserved_at_40[0x40];
4580 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4581 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4585 u8 opcode[0x10];
4586 u8 reserved_at_10[0x10];
4588 u8 reserved_at_20[0x10];
4589 u8 op_mod[0x10];
4591 u8 reserved_at_40[0x20];
4593 u8 reserved_at_60[0x6];
4594 u8 demux_mode[0x2];
4595 u8 reserved_at_68[0x18];
4599 u8 status[0x8];
4600 u8 reserved_at_8[0x18];
4602 u8 syndrome[0x20];
4604 u8 reserved_at_40[0x40];
4608 u8 opcode[0x10];
4609 u8 reserved_at_10[0x10];
4611 u8 reserved_at_20[0x10];
4612 u8 op_mod[0x10];
4614 u8 reserved_at_40[0x60];
4616 u8 reserved_at_a0[0x8];
4617 u8 table_index[0x18];
4619 u8 reserved_at_c0[0x20];
4621 u8 reserved_at_e0[0x13];
4622 u8 vlan_valid[0x1];
4623 u8 vlan[0xc];
4627 u8 reserved_at_140[0xc0];
4631 u8 status[0x8];
4632 u8 reserved_at_8[0x18];
4634 u8 syndrome[0x20];
4636 u8 reserved_at_40[0x40];
4640 u8 opcode[0x10];
4641 u8 reserved_at_10[0x10];
4643 u8 reserved_at_20[0x10];
4644 u8 op_mod[0x10];
4646 u8 reserved_at_40[0x10];
4647 u8 current_issi[0x10];
4649 u8 reserved_at_60[0x20];
4653 u8 status[0x8];
4654 u8 reserved_at_8[0x18];
4656 u8 syndrome[0x20];
4658 u8 reserved_at_40[0x40];
4662 u8 opcode[0x10];
4663 u8 reserved_at_10[0x10];
4665 u8 reserved_at_20[0x10];
4666 u8 op_mod[0x10];
4668 u8 other_function[0x1];
4669 u8 reserved_at_41[0xf];
4670 u8 function_id[0x10];
4672 u8 reserved_at_60[0x20];
4678 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4679 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4680 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
4681 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4682 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
4686 u8 status[0x8];
4687 u8 reserved_at_8[0x18];
4689 u8 syndrome[0x20];
4691 u8 reserved_at_40[0x40];
4695 u8 opcode[0x10];
4696 u8 reserved_at_10[0x10];
4698 u8 reserved_at_20[0x10];
4699 u8 op_mod[0x10];
4701 u8 other_vport[0x1];
4702 u8 reserved_at_41[0xf];
4703 u8 vport_number[0x10];
4705 u8 reserved_at_60[0x20];
4707 u8 table_type[0x8];
4708 u8 reserved_at_88[0x18];
4710 u8 reserved_at_a0[0x8];
4711 u8 table_id[0x18];
4713 u8 ignore_flow_level[0x1];
4714 u8 reserved_at_c1[0x17];
4715 u8 modify_enable_mask[0x8];
4717 u8 reserved_at_e0[0x20];
4719 u8 flow_index[0x20];
4721 u8 reserved_at_120[0xe0];
4727 u8 status[0x8];
4728 u8 reserved_at_8[0x18];
4730 u8 syndrome[0x20];
4732 u8 reserved_at_40[0x20];
4733 u8 ece[0x20];
4737 u8 opcode[0x10];
4738 u8 uid[0x10];
4740 u8 reserved_at_20[0x10];
4741 u8 op_mod[0x10];
4743 u8 reserved_at_40[0x8];
4744 u8 qpn[0x18];
4746 u8 reserved_at_60[0x20];
4748 u8 opt_param_mask[0x20];
4750 u8 ece[0x20];
4754 u8 reserved_at_800[0x80];
4758 u8 status[0x8];
4759 u8 reserved_at_8[0x18];
4761 u8 syndrome[0x20];
4763 u8 reserved_at_40[0x20];
4764 u8 ece[0x20];
4768 u8 opcode[0x10];
4769 u8 uid[0x10];
4771 u8 reserved_at_20[0x10];
4772 u8 op_mod[0x10];
4774 u8 reserved_at_40[0x8];
4775 u8 qpn[0x18];
4777 u8 reserved_at_60[0x20];
4779 u8 opt_param_mask[0x20];
4781 u8 ece[0x20];
4785 u8 reserved_at_800[0x80];
4789 u8 status[0x8];
4790 u8 reserved_at_8[0x18];
4792 u8 syndrome[0x20];
4794 u8 reserved_at_40[0x20];
4795 u8 ece[0x20];
4799 u8 opcode[0x10];
4800 u8 uid[0x10];
4802 u8 reserved_at_20[0x10];
4803 u8 op_mod[0x10];
4805 u8 reserved_at_40[0x8];
4806 u8 qpn[0x18];
4808 u8 reserved_at_60[0x20];
4810 u8 opt_param_mask[0x20];
4812 u8 ece[0x20];
4816 u8 reserved_at_800[0x80];
4820 u8 status[0x8];
4821 u8 reserved_at_8[0x18];
4823 u8 syndrome[0x20];
4825 u8 reserved_at_40[0x40];
4831 u8 opcode[0x10];
4832 u8 reserved_at_10[0x10];
4834 u8 reserved_at_20[0x10];
4835 u8 op_mod[0x10];
4837 u8 reserved_at_40[0x8];
4838 u8 xrqn[0x18];
4840 u8 reserved_at_60[0x20];
4844 u8 status[0x8];
4845 u8 reserved_at_8[0x18];
4847 u8 syndrome[0x20];
4849 u8 reserved_at_40[0x40];
4853 u8 reserved_at_280[0x600];
4855 u8 pas[][0x40];
4859 u8 opcode[0x10];
4860 u8 reserved_at_10[0x10];
4862 u8 reserved_at_20[0x10];
4863 u8 op_mod[0x10];
4865 u8 reserved_at_40[0x8];
4866 u8 xrc_srqn[0x18];
4868 u8 reserved_at_60[0x20];
4872 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4873 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4877 u8 status[0x8];
4878 u8 reserved_at_8[0x18];
4880 u8 syndrome[0x20];
4882 u8 reserved_at_40[0x20];
4884 u8 reserved_at_60[0x18];
4885 u8 admin_state[0x4];
4886 u8 state[0x4];
4890 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4891 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4892 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
4896 u8 opcode[0x10];
4897 u8 uid[0x10];
4899 u8 reserved_at_20[0x10];
4900 u8 op_mod[0x10];
4902 u8 reserved_at_40[0x20];
4904 u8 reserved_at_60[0x20];
4908 u8 status[0x8];
4909 u8 reserved_at_8[0x18];
4911 u8 syndrome[0x20];
4913 u8 reserved_at_40[0x40];
4917 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4918 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4922 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4923 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4924 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4925 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4926 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4927 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4931 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4935 u8 reserved_at_0[0x4];
4936 u8 type[0x4];
4937 u8 reserved_at_8[0x8];
4938 u8 counter[0x10];
4940 u8 counter_group_id[0x20];
4949 u8 opcode[0x10];
4950 u8 uid[0x10];
4952 u8 reserved_at_20[0x10];
4953 u8 op_mod[0x10];
4955 u8 reserved_at_40[0x10];
4956 u8 num_of_counters[0x10];
4958 u8 reserved_at_60[0x20];
4964 u8 status[0x8];
4965 u8 reserved_at_8[0x18];
4967 u8 syndrome[0x20];
4969 u8 reserved_at_40[0x40];
4973 u8 opcode[0x10];
4974 u8 reserved_at_10[0x10];
4976 u8 reserved_at_20[0x10];
4977 u8 op_mod[0x10];
4979 u8 other_vport[0x1];
4980 u8 reserved_at_41[0xf];
4981 u8 vport_number[0x10];
4983 u8 reserved_at_60[0x20];
4987 u8 status[0x8];
4988 u8 reserved_at_8[0x18];
4990 u8 syndrome[0x20];
4992 u8 reserved_at_40[0x40];
4998 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
5002 u8 opcode[0x10];
5003 u8 reserved_at_10[0x10];
5005 u8 reserved_at_20[0x10];
5006 u8 op_mod[0x10];
5008 u8 other_vport[0x1];
5009 u8 reserved_at_41[0xf];
5010 u8 vport_number[0x10];
5012 u8 reserved_at_60[0x20];
5016 u8 status[0x8];
5017 u8 reserved_at_8[0x18];
5019 u8 syndrome[0x20];
5021 u8 reserved_at_40[0x40];
5047 u8 reserved_at_680[0xa00];
5051 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
5055 u8 opcode[0x10];
5056 u8 reserved_at_10[0x10];
5058 u8 reserved_at_20[0x10];
5059 u8 op_mod[0x10];
5061 u8 other_vport[0x1];
5062 u8 reserved_at_41[0xb];
5063 u8 port_num[0x4];
5064 u8 vport_number[0x10];
5066 u8 reserved_at_60[0x60];
5068 u8 clear[0x1];
5069 u8 reserved_at_c1[0x1f];
5071 u8 reserved_at_e0[0x20];
5075 u8 status[0x8];
5076 u8 reserved_at_8[0x18];
5078 u8 syndrome[0x20];
5080 u8 reserved_at_40[0x40];
5086 u8 opcode[0x10];
5087 u8 reserved_at_10[0x10];
5089 u8 reserved_at_20[0x10];
5090 u8 op_mod[0x10];
5092 u8 reserved_at_40[0x8];
5093 u8 tisn[0x18];
5095 u8 reserved_at_60[0x20];
5099 u8 status[0x8];
5100 u8 reserved_at_8[0x18];
5102 u8 syndrome[0x20];
5104 u8 reserved_at_40[0xc0];
5110 u8 opcode[0x10];
5111 u8 reserved_at_10[0x10];
5113 u8 reserved_at_20[0x10];
5114 u8 op_mod[0x10];
5116 u8 reserved_at_40[0x8];
5117 u8 tirn[0x18];
5119 u8 reserved_at_60[0x20];
5123 u8 status[0x8];
5124 u8 reserved_at_8[0x18];
5126 u8 syndrome[0x20];
5128 u8 reserved_at_40[0x40];
5132 u8 reserved_at_280[0x600];
5134 u8 pas[][0x40];
5138 u8 opcode[0x10];
5139 u8 reserved_at_10[0x10];
5141 u8 reserved_at_20[0x10];
5142 u8 op_mod[0x10];
5144 u8 reserved_at_40[0x8];
5145 u8 srqn[0x18];
5147 u8 reserved_at_60[0x20];
5151 u8 status[0x8];
5152 u8 reserved_at_8[0x18];
5154 u8 syndrome[0x20];
5156 u8 reserved_at_40[0xc0];
5162 u8 opcode[0x10];
5163 u8 reserved_at_10[0x10];
5165 u8 reserved_at_20[0x10];
5166 u8 op_mod[0x10];
5168 u8 reserved_at_40[0x8];
5169 u8 sqn[0x18];
5171 u8 reserved_at_60[0x20];
5175 u8 status[0x8];
5176 u8 reserved_at_8[0x18];
5178 u8 syndrome[0x20];
5180 u8 dump_fill_mkey[0x20];
5182 u8 resd_lkey[0x20];
5184 u8 null_mkey[0x20];
5186 u8 reserved_at_a0[0x60];
5190 u8 opcode[0x10];
5191 u8 reserved_at_10[0x10];
5193 u8 reserved_at_20[0x10];
5194 u8 op_mod[0x10];
5196 u8 reserved_at_40[0x40];
5200 u8 opcode[0x10];
5201 u8 reserved_at_10[0x10];
5203 u8 reserved_at_20[0x10];
5204 u8 op_mod[0x10];
5206 u8 reserved_at_40[0xc0];
5210 u8 reserved_at_300[0x100];
5214 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5215 SCHEDULING_HIERARCHY_NIC = 0x3,
5219 u8 opcode[0x10];
5220 u8 reserved_at_10[0x10];
5222 u8 reserved_at_20[0x10];
5223 u8 op_mod[0x10];
5225 u8 scheduling_hierarchy[0x8];
5226 u8 reserved_at_48[0x18];
5228 u8 scheduling_element_id[0x20];
5230 u8 reserved_at_80[0x180];
5234 u8 status[0x8];
5235 u8 reserved_at_8[0x18];
5237 u8 syndrome[0x20];
5239 u8 reserved_at_40[0xc0];
5245 u8 opcode[0x10];
5246 u8 reserved_at_10[0x10];
5248 u8 reserved_at_20[0x10];
5249 u8 op_mod[0x10];
5251 u8 reserved_at_40[0x8];
5252 u8 rqtn[0x18];
5254 u8 reserved_at_60[0x20];
5258 u8 status[0x8];
5259 u8 reserved_at_8[0x18];
5261 u8 syndrome[0x20];
5263 u8 reserved_at_40[0xc0];
5269 u8 opcode[0x10];
5270 u8 reserved_at_10[0x10];
5272 u8 reserved_at_20[0x10];
5273 u8 op_mod[0x10];
5275 u8 reserved_at_40[0x8];
5276 u8 rqn[0x18];
5278 u8 reserved_at_60[0x20];
5282 u8 status[0x8];
5283 u8 reserved_at_8[0x18];
5285 u8 syndrome[0x20];
5287 u8 reserved_at_40[0x40];
5293 u8 opcode[0x10];
5294 u8 reserved_at_10[0x10];
5296 u8 reserved_at_20[0x10];
5297 u8 op_mod[0x10];
5299 u8 roce_address_index[0x10];
5300 u8 reserved_at_50[0xc];
5301 u8 vhca_port_num[0x4];
5303 u8 reserved_at_60[0x20];
5307 u8 status[0x8];
5308 u8 reserved_at_8[0x18];
5310 u8 syndrome[0x20];
5312 u8 reserved_at_40[0xc0];
5318 u8 opcode[0x10];
5319 u8 reserved_at_10[0x10];
5321 u8 reserved_at_20[0x10];
5322 u8 op_mod[0x10];
5324 u8 reserved_at_40[0x8];
5325 u8 rmpn[0x18];
5327 u8 reserved_at_60[0x20];
5331 u8 status[0x8];
5332 u8 reserved_at_8[0x18];
5334 u8 syndrome[0x20];
5336 u8 reserved_at_40[0x40];
5338 u8 opt_param_mask[0x20];
5340 u8 ece[0x20];
5344 u8 reserved_at_800[0x80];
5346 u8 pas[][0x40];
5350 u8 opcode[0x10];
5351 u8 reserved_at_10[0x10];
5353 u8 reserved_at_20[0x10];
5354 u8 op_mod[0x10];
5356 u8 reserved_at_40[0x8];
5357 u8 qpn[0x18];
5359 u8 reserved_at_60[0x20];
5363 u8 status[0x8];
5364 u8 reserved_at_8[0x18];
5366 u8 syndrome[0x20];
5368 u8 reserved_at_40[0x40];
5370 u8 rx_write_requests[0x20];
5372 u8 reserved_at_a0[0x20];
5374 u8 rx_read_requests[0x20];
5376 u8 reserved_at_e0[0x20];
5378 u8 rx_atomic_requests[0x20];
5380 u8 reserved_at_120[0x20];
5382 u8 rx_dct_connect[0x20];
5384 u8 reserved_at_160[0x20];
5386 u8 out_of_buffer[0x20];
5388 u8 reserved_at_1a0[0x20];
5390 u8 out_of_sequence[0x20];
5392 u8 reserved_at_1e0[0x20];
5394 u8 duplicate_request[0x20];
5396 u8 reserved_at_220[0x20];
5398 u8 rnr_nak_retry_err[0x20];
5400 u8 reserved_at_260[0x20];
5402 u8 packet_seq_err[0x20];
5404 u8 reserved_at_2a0[0x20];
5406 u8 implied_nak_seq_err[0x20];
5408 u8 reserved_at_2e0[0x20];
5410 u8 local_ack_timeout_err[0x20];
5412 u8 reserved_at_320[0xa0];
5414 u8 resp_local_length_error[0x20];
5416 u8 req_local_length_error[0x20];
5418 u8 resp_local_qp_error[0x20];
5420 u8 local_operation_error[0x20];
5422 u8 resp_local_protection[0x20];
5424 u8 req_local_protection[0x20];
5426 u8 resp_cqe_error[0x20];
5428 u8 req_cqe_error[0x20];
5430 u8 req_mw_binding[0x20];
5432 u8 req_bad_response[0x20];
5434 u8 req_remote_invalid_request[0x20];
5436 u8 resp_remote_invalid_request[0x20];
5438 u8 req_remote_access_errors[0x20];
5440 u8 resp_remote_access_errors[0x20];
5442 u8 req_remote_operation_errors[0x20];
5444 u8 req_transport_retries_exceeded[0x20];
5446 u8 cq_overflow[0x20];
5448 u8 resp_cqe_flush_error[0x20];
5450 u8 req_cqe_flush_error[0x20];
5452 u8 reserved_at_620[0x20];
5454 u8 roce_adp_retrans[0x20];
5456 u8 roce_adp_retrans_to[0x20];
5458 u8 roce_slow_restart[0x20];
5460 u8 roce_slow_restart_cnps[0x20];
5462 u8 roce_slow_restart_trans[0x20];
5464 u8 reserved_at_6e0[0x120];
5468 u8 opcode[0x10];
5469 u8 reserved_at_10[0x10];
5471 u8 reserved_at_20[0x10];
5472 u8 op_mod[0x10];
5474 u8 reserved_at_40[0x80];
5476 u8 clear[0x1];
5477 u8 reserved_at_c1[0x1f];
5479 u8 reserved_at_e0[0x18];
5480 u8 counter_set_id[0x8];
5484 u8 status[0x8];
5485 u8 reserved_at_8[0x18];
5487 u8 syndrome[0x20];
5489 u8 embedded_cpu_function[0x1];
5490 u8 reserved_at_41[0xf];
5491 u8 function_id[0x10];
5493 u8 num_pages[0x20];
5497 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5498 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5499 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5503 u8 opcode[0x10];
5504 u8 reserved_at_10[0x10];
5506 u8 reserved_at_20[0x10];
5507 u8 op_mod[0x10];
5509 u8 embedded_cpu_function[0x1];
5510 u8 reserved_at_41[0xf];
5511 u8 function_id[0x10];
5513 u8 reserved_at_60[0x20];
5517 u8 status[0x8];
5518 u8 reserved_at_8[0x18];
5520 u8 syndrome[0x20];
5522 u8 reserved_at_40[0x40];
5528 u8 opcode[0x10];
5529 u8 reserved_at_10[0x10];
5531 u8 reserved_at_20[0x10];
5532 u8 op_mod[0x10];
5534 u8 other_vport[0x1];
5535 u8 reserved_at_41[0xf];
5536 u8 vport_number[0x10];
5538 u8 reserved_at_60[0x5];
5539 u8 allowed_list_type[0x3];
5540 u8 reserved_at_68[0x18];
5544 u8 status[0x8];
5545 u8 reserved_at_8[0x18];
5547 u8 syndrome[0x20];
5549 u8 reserved_at_40[0x40];
5553 u8 reserved_at_280[0x600];
5555 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5557 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5561 u8 opcode[0x10];
5562 u8 reserved_at_10[0x10];
5564 u8 reserved_at_20[0x10];
5565 u8 op_mod[0x10];
5567 u8 reserved_at_40[0x8];
5568 u8 mkey_index[0x18];
5570 u8 pg_access[0x1];
5571 u8 reserved_at_61[0x1f];
5575 u8 status[0x8];
5576 u8 reserved_at_8[0x18];
5578 u8 syndrome[0x20];
5580 u8 reserved_at_40[0x40];
5582 u8 mad_dumux_parameters_block[0x20];
5586 u8 opcode[0x10];
5587 u8 reserved_at_10[0x10];
5589 u8 reserved_at_20[0x10];
5590 u8 op_mod[0x10];
5592 u8 reserved_at_40[0x40];
5596 u8 status[0x8];
5597 u8 reserved_at_8[0x18];
5599 u8 syndrome[0x20];
5601 u8 reserved_at_40[0xa0];
5603 u8 reserved_at_e0[0x13];
5604 u8 vlan_valid[0x1];
5605 u8 vlan[0xc];
5609 u8 reserved_at_140[0xc0];
5613 u8 opcode[0x10];
5614 u8 reserved_at_10[0x10];
5616 u8 reserved_at_20[0x10];
5617 u8 op_mod[0x10];
5619 u8 reserved_at_40[0x60];
5621 u8 reserved_at_a0[0x8];
5622 u8 table_index[0x18];
5624 u8 reserved_at_c0[0x140];
5628 u8 status[0x8];
5629 u8 reserved_at_8[0x18];
5631 u8 syndrome[0x20];
5633 u8 reserved_at_40[0x10];
5634 u8 current_issi[0x10];
5636 u8 reserved_at_60[0xa0];
5638 u8 reserved_at_100[76][0x8];
5639 u8 supported_issi_dw0[0x20];
5643 u8 opcode[0x10];
5644 u8 reserved_at_10[0x10];
5646 u8 reserved_at_20[0x10];
5647 u8 op_mod[0x10];
5649 u8 reserved_at_40[0x40];
5653 u8 status[0x8];
5654 u8 reserved_0[0x18];
5656 u8 syndrome[0x20];
5657 u8 reserved_1[0x40];
5661 u8 opcode[0x10];
5662 u8 reserved_0[0x10];
5664 u8 reserved_1[0x10];
5665 u8 op_mod[0x10];
5667 u8 reserved_2[0x40];
5668 u8 driver_version[64][0x8];
5672 u8 status[0x8];
5673 u8 reserved_at_8[0x18];
5675 u8 syndrome[0x20];
5677 u8 reserved_at_40[0x40];
5683 u8 opcode[0x10];
5684 u8 reserved_at_10[0x10];
5686 u8 reserved_at_20[0x10];
5687 u8 op_mod[0x10];
5689 u8 other_vport[0x1];
5690 u8 reserved_at_41[0xb];
5691 u8 port_num[0x4];
5692 u8 vport_number[0x10];
5694 u8 reserved_at_60[0x10];
5695 u8 pkey_index[0x10];
5699 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5705 u8 status[0x8];
5706 u8 reserved_at_8[0x18];
5708 u8 syndrome[0x20];
5710 u8 reserved_at_40[0x20];
5712 u8 gids_num[0x10];
5713 u8 reserved_at_70[0x10];
5719 u8 opcode[0x10];
5720 u8 reserved_at_10[0x10];
5722 u8 reserved_at_20[0x10];
5723 u8 op_mod[0x10];
5725 u8 other_vport[0x1];
5726 u8 reserved_at_41[0xb];
5727 u8 port_num[0x4];
5728 u8 vport_number[0x10];
5730 u8 reserved_at_60[0x10];
5731 u8 gid_index[0x10];
5735 u8 status[0x8];
5736 u8 reserved_at_8[0x18];
5738 u8 syndrome[0x20];
5740 u8 reserved_at_40[0x40];
5746 u8 opcode[0x10];
5747 u8 reserved_at_10[0x10];
5749 u8 reserved_at_20[0x10];
5750 u8 op_mod[0x10];
5752 u8 other_vport[0x1];
5753 u8 reserved_at_41[0xb];
5754 u8 port_num[0x4];
5755 u8 vport_number[0x10];
5757 u8 reserved_at_60[0x20];
5761 u8 status[0x8];
5762 u8 reserved_at_8[0x18];
5764 u8 syndrome[0x20];
5766 u8 reserved_at_40[0x40];
5772 u8 opcode[0x10];
5773 u8 reserved_at_10[0x10];
5775 u8 reserved_at_20[0x10];
5776 u8 op_mod[0x10];
5778 u8 other_function[0x1];
5779 u8 reserved_at_41[0xf];
5780 u8 function_id[0x10];
5782 u8 reserved_at_60[0x20];
5786 u8 roce[0x1];
5787 u8 reserved_at_1[0x27f];
5791 u8 status[0x8];
5792 u8 reserved_at_8[0x18];
5794 u8 syndrome[0x20];
5796 u8 reserved_at_40[0x40];
5802 u8 opcode[0x10];
5803 u8 reserved_at_10[0x10];
5805 u8 reserved_at_20[0x10];
5806 u8 op_mod[0x10];
5808 u8 reserved_at_40[0x10];
5809 u8 function_id[0x10];
5811 u8 reserved_at_60[0x20];
5815 u8 status[0x8];
5816 u8 reserved_at_8[0x18];
5818 u8 syndrome[0x20];
5820 u8 reserved_at_40[0x40];
5824 u8 opcode[0x10];
5825 u8 reserved_at_10[0x10];
5827 u8 reserved_at_20[0x10];
5828 u8 op_mod[0x10];
5830 u8 reserved_at_40[0x10];
5831 u8 function_id[0x10];
5832 u8 field_select[0x20];
5838 u8 reformat_en[0x1];
5839 u8 decap_en[0x1];
5840 u8 sw_owner[0x1];
5841 u8 termination_table[0x1];
5842 u8 table_miss_action[0x4];
5843 u8 level[0x8];
5844 u8 reserved_at_10[0x8];
5845 u8 log_size[0x8];
5847 u8 reserved_at_20[0x8];
5848 u8 table_miss_id[0x18];
5850 u8 reserved_at_40[0x8];
5851 u8 lag_master_next_table_id[0x18];
5853 u8 reserved_at_60[0x60];
5855 u8 sw_owner_icm_root_1[0x40];
5857 u8 sw_owner_icm_root_0[0x40];
5862 u8 status[0x8];
5863 u8 reserved_at_8[0x18];
5865 u8 syndrome[0x20];
5867 u8 reserved_at_40[0x80];
5873 u8 opcode[0x10];
5874 u8 reserved_at_10[0x10];
5876 u8 reserved_at_20[0x10];
5877 u8 op_mod[0x10];
5879 u8 reserved_at_40[0x40];
5881 u8 table_type[0x8];
5882 u8 reserved_at_88[0x18];
5884 u8 reserved_at_a0[0x8];
5885 u8 table_id[0x18];
5887 u8 reserved_at_c0[0x140];
5891 u8 status[0x8];
5892 u8 reserved_at_8[0x18];
5894 u8 syndrome[0x20];
5896 u8 reserved_at_40[0x1c0];
5902 u8 opcode[0x10];
5903 u8 reserved_at_10[0x10];
5905 u8 reserved_at_20[0x10];
5906 u8 op_mod[0x10];
5908 u8 reserved_at_40[0x40];
5910 u8 table_type[0x8];
5911 u8 reserved_at_88[0x18];
5913 u8 reserved_at_a0[0x8];
5914 u8 table_id[0x18];
5916 u8 reserved_at_c0[0x40];
5918 u8 flow_index[0x20];
5920 u8 reserved_at_120[0xe0];
5924 u8 reserved_at_0[0x100];
5926 u8 metadata_reg_c_0[0x20];
5928 u8 metadata_reg_c_1[0x20];
5930 u8 outer_dmac_47_16[0x20];
5932 u8 outer_dmac_15_0[0x10];
5933 u8 outer_ethertype[0x10];
5935 u8 reserved_at_180[0x1];
5936 u8 sx_sniffer[0x1];
5937 u8 functional_lb[0x1];
5938 u8 outer_ip_frag[0x1];
5939 u8 outer_qp_type[0x2];
5940 u8 outer_encap_type[0x2];
5941 u8 port_number[0x2];
5942 u8 outer_l3_type[0x2];
5943 u8 outer_l4_type[0x2];
5944 u8 outer_first_vlan_type[0x2];
5945 u8 outer_first_vlan_prio[0x3];
5946 u8 outer_first_vlan_cfi[0x1];
5947 u8 outer_first_vlan_vid[0xc];
5949 u8 outer_l4_type_ext[0x4];
5950 u8 reserved_at_1a4[0x2];
5951 u8 outer_ipsec_layer[0x2];
5952 u8 outer_l2_type[0x2];
5953 u8 force_lb[0x1];
5954 u8 outer_l2_ok[0x1];
5955 u8 outer_l3_ok[0x1];
5956 u8 outer_l4_ok[0x1];
5957 u8 outer_second_vlan_type[0x2];
5958 u8 outer_second_vlan_prio[0x3];
5959 u8 outer_second_vlan_cfi[0x1];
5960 u8 outer_second_vlan_vid[0xc];
5962 u8 outer_smac_47_16[0x20];
5964 u8 outer_smac_15_0[0x10];
5965 u8 inner_ipv4_checksum_ok[0x1];
5966 u8 inner_l4_checksum_ok[0x1];
5967 u8 outer_ipv4_checksum_ok[0x1];
5968 u8 outer_l4_checksum_ok[0x1];
5969 u8 inner_l3_ok[0x1];
5970 u8 inner_l4_ok[0x1];
5971 u8 outer_l3_ok_duplicate[0x1];
5972 u8 outer_l4_ok_duplicate[0x1];
5973 u8 outer_tcp_cwr[0x1];
5974 u8 outer_tcp_ece[0x1];
5975 u8 outer_tcp_urg[0x1];
5976 u8 outer_tcp_ack[0x1];
5977 u8 outer_tcp_psh[0x1];
5978 u8 outer_tcp_rst[0x1];
5979 u8 outer_tcp_syn[0x1];
5980 u8 outer_tcp_fin[0x1];
5984 u8 reserved_at_0[0x100];
5986 u8 outer_ip_src_addr[0x20];
5988 u8 outer_ip_dest_addr[0x20];
5990 u8 outer_l4_sport[0x10];
5991 u8 outer_l4_dport[0x10];
5993 u8 reserved_at_160[0x1];
5994 u8 sx_sniffer[0x1];
5995 u8 functional_lb[0x1];
5996 u8 outer_ip_frag[0x1];
5997 u8 outer_qp_type[0x2];
5998 u8 outer_encap_type[0x2];
5999 u8 port_number[0x2];
6000 u8 outer_l3_type[0x2];
6001 u8 outer_l4_type[0x2];
6002 u8 outer_first_vlan_type[0x2];
6003 u8 outer_first_vlan_prio[0x3];
6004 u8 outer_first_vlan_cfi[0x1];
6005 u8 outer_first_vlan_vid[0xc];
6007 u8 metadata_reg_c_0[0x20];
6009 u8 outer_dmac_47_16[0x20];
6011 u8 outer_smac_47_16[0x20];
6013 u8 outer_smac_15_0[0x10];
6014 u8 outer_dmac_15_0[0x10];
6018 u8 reserved_at_0[0x100];
6020 u8 inner_ip_src_addr[0x20];
6022 u8 inner_ip_dest_addr[0x20];
6024 u8 inner_l4_sport[0x10];
6025 u8 inner_l4_dport[0x10];
6027 u8 reserved_at_160[0x1];
6028 u8 sx_sniffer[0x1];
6029 u8 functional_lb[0x1];
6030 u8 inner_ip_frag[0x1];
6031 u8 inner_qp_type[0x2];
6032 u8 inner_encap_type[0x2];
6033 u8 port_number[0x2];
6034 u8 inner_l3_type[0x2];
6035 u8 inner_l4_type[0x2];
6036 u8 inner_first_vlan_type[0x2];
6037 u8 inner_first_vlan_prio[0x3];
6038 u8 inner_first_vlan_cfi[0x1];
6039 u8 inner_first_vlan_vid[0xc];
6041 u8 tunnel_header_0[0x20];
6043 u8 inner_dmac_47_16[0x20];
6045 u8 inner_smac_47_16[0x20];
6047 u8 inner_smac_15_0[0x10];
6048 u8 inner_dmac_15_0[0x10];
6052 u8 reserved_at_0[0xc0];
6054 u8 outer_ip_dest_addr[0x80];
6056 u8 outer_ip_src_addr[0x80];
6058 u8 outer_l4_sport[0x10];
6059 u8 outer_l4_dport[0x10];
6061 u8 reserved_at_1e0[0x20];
6065 u8 reserved_at_0[0xa0];
6067 u8 outer_ip_dest_addr[0x80];
6069 u8 outer_ip_src_addr[0x80];
6071 u8 outer_dmac_47_16[0x20];
6073 u8 outer_smac_47_16[0x20];
6075 u8 outer_smac_15_0[0x10];
6076 u8 outer_dmac_15_0[0x10];
6080 u8 reserved_at_0[0xc0];
6082 u8 inner_ip_dest_addr[0x80];
6084 u8 inner_ip_src_addr[0x80];
6086 u8 inner_l4_sport[0x10];
6087 u8 inner_l4_dport[0x10];
6089 u8 reserved_at_1e0[0x20];
6093 u8 reserved_at_0[0xa0];
6095 u8 inner_ip_dest_addr[0x80];
6097 u8 inner_ip_src_addr[0x80];
6099 u8 inner_dmac_47_16[0x20];
6101 u8 inner_smac_47_16[0x20];
6103 u8 inner_smac_15_0[0x10];
6104 u8 inner_dmac_15_0[0x10];
6108 u8 modify_field_select[0x40];
6110 u8 reserved_at_40[0x40];
6112 u8 reserved_at_80[0x10];
6113 u8 format_id[0x10];
6115 u8 reserved_at_a0[0x160];
6117 u8 match_mask[16][0x20];
6121 u8 opcode[0x10];
6122 u8 uid[0x10];
6124 u8 vhca_tunnel_id[0x10];
6125 u8 obj_type[0x10];
6127 u8 obj_id[0x20];
6129 u8 reserved_at_60[0x3];
6130 u8 log_obj_range[0x5];
6131 u8 reserved_at_68[0x18];
6135 u8 status[0x8];
6136 u8 reserved_at_8[0x18];
6138 u8 syndrome[0x20];
6140 u8 obj_id[0x20];
6142 u8 reserved_at_60[0x20];
6156 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6157 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6158 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6159 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6160 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6161 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6162 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6166 u8 status[0x8];
6167 u8 reserved_at_8[0x18];
6169 u8 syndrome[0x20];
6171 u8 reserved_at_40[0xa0];
6173 u8 start_flow_index[0x20];
6175 u8 reserved_at_100[0x20];
6177 u8 end_flow_index[0x20];
6179 u8 reserved_at_140[0xa0];
6181 u8 reserved_at_1e0[0x18];
6182 u8 match_criteria_enable[0x8];
6186 u8 reserved_at_1200[0xe00];
6190 u8 opcode[0x10];
6191 u8 reserved_at_10[0x10];
6193 u8 reserved_at_20[0x10];
6194 u8 op_mod[0x10];
6196 u8 reserved_at_40[0x40];
6198 u8 table_type[0x8];
6199 u8 reserved_at_88[0x18];
6201 u8 reserved_at_a0[0x8];
6202 u8 table_id[0x18];
6204 u8 group_id[0x20];
6206 u8 reserved_at_e0[0x120];
6210 u8 status[0x8];
6211 u8 reserved_at_8[0x18];
6213 u8 syndrome[0x20];
6215 u8 reserved_at_40[0x40];
6221 u8 opcode[0x10];
6222 u8 reserved_at_10[0x10];
6224 u8 reserved_at_20[0x10];
6225 u8 op_mod[0x10];
6227 u8 reserved_at_40[0x80];
6229 u8 clear[0x1];
6230 u8 reserved_at_c1[0xf];
6231 u8 num_of_counters[0x10];
6233 u8 flow_counter_id[0x20];
6237 u8 status[0x8];
6238 u8 reserved_at_8[0x18];
6240 u8 syndrome[0x20];
6242 u8 reserved_at_40[0x40];
6248 u8 opcode[0x10];
6249 u8 reserved_at_10[0x10];
6251 u8 reserved_at_20[0x10];
6252 u8 op_mod[0x10];
6254 u8 other_vport[0x1];
6255 u8 reserved_at_41[0xf];
6256 u8 vport_number[0x10];
6258 u8 reserved_at_60[0x20];
6262 u8 status[0x8];
6263 u8 reserved_at_8[0x18];
6265 u8 syndrome[0x20];
6267 u8 reserved_at_40[0x40];
6271 u8 reserved_at_0[0x1b];
6272 u8 fdb_to_vport_reg_c_id[0x1];
6273 u8 vport_cvlan_insert[0x1];
6274 u8 vport_svlan_insert[0x1];
6275 u8 vport_cvlan_strip[0x1];
6276 u8 vport_svlan_strip[0x1];
6280 u8 opcode[0x10];
6281 u8 reserved_at_10[0x10];
6283 u8 reserved_at_20[0x10];
6284 u8 op_mod[0x10];
6286 u8 other_vport[0x1];
6287 u8 reserved_at_41[0xf];
6288 u8 vport_number[0x10];
6296 u8 status[0x8];
6297 u8 reserved_at_8[0x18];
6299 u8 syndrome[0x20];
6301 u8 reserved_at_40[0x40];
6305 u8 reserved_at_280[0x40];
6307 u8 event_bitmask[0x40];
6309 u8 reserved_at_300[0x580];
6311 u8 pas[][0x40];
6315 u8 opcode[0x10];
6316 u8 reserved_at_10[0x10];
6318 u8 reserved_at_20[0x10];
6319 u8 op_mod[0x10];
6321 u8 reserved_at_40[0x18];
6322 u8 eq_number[0x8];
6324 u8 reserved_at_60[0x20];
6328 u8 reformat_type[0x8];
6329 u8 reserved_at_8[0x4];
6330 u8 reformat_param_0[0x4];
6331 u8 reserved_at_10[0x6];
6332 u8 reformat_data_size[0xa];
6334 u8 reformat_param_1[0x8];
6335 u8 reserved_at_28[0x8];
6336 u8 reformat_data[2][0x8];
6338 u8 more_reformat_data[][0x8];
6342 u8 status[0x8];
6343 u8 reserved_at_8[0x18];
6345 u8 syndrome[0x20];
6347 u8 reserved_at_40[0xa0];
6353 u8 opcode[0x10];
6354 u8 reserved_at_10[0x10];
6356 u8 reserved_at_20[0x10];
6357 u8 op_mod[0x10];
6359 u8 packet_reformat_id[0x20];
6361 u8 reserved_at_60[0xa0];
6365 u8 status[0x8];
6366 u8 reserved_at_8[0x18];
6368 u8 syndrome[0x20];
6370 u8 packet_reformat_id[0x20];
6372 u8 reserved_at_60[0x20];
6376 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6377 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6378 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6382 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6383 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6384 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6385 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6386 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6387 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6388 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6389 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6390 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
6394 u8 opcode[0x10];
6395 u8 reserved_at_10[0x10];
6397 u8 reserved_at_20[0x10];
6398 u8 op_mod[0x10];
6400 u8 reserved_at_40[0xa0];
6406 u8 status[0x8];
6407 u8 reserved_at_8[0x18];
6409 u8 syndrome[0x20];
6411 u8 reserved_at_40[0x40];
6415 u8 opcode[0x10];
6416 u8 reserved_at_10[0x10];
6418 u8 reserved_20[0x10];
6419 u8 op_mod[0x10];
6421 u8 packet_reformat_id[0x20];
6423 u8 reserved_60[0x20];
6427 u8 action_type[0x4];
6428 u8 field[0xc];
6429 u8 reserved_at_10[0x3];
6430 u8 offset[0x5];
6431 u8 reserved_at_18[0x3];
6432 u8 length[0x5];
6434 u8 data[0x20];
6438 u8 action_type[0x4];
6439 u8 field[0xc];
6440 u8 reserved_at_10[0x10];
6442 u8 data[0x20];
6446 u8 action_type[0x4];
6447 u8 src_field[0xc];
6448 u8 reserved_at_10[0x3];
6449 u8 src_offset[0x5];
6450 u8 reserved_at_18[0x3];
6451 u8 length[0x5];
6453 u8 reserved_at_20[0x4];
6454 u8 dst_field[0xc];
6455 u8 reserved_at_30[0x3];
6456 u8 dst_offset[0x5];
6457 u8 reserved_at_38[0x8];
6464 u8 reserved_at_0[0x40];
6468 MLX5_ACTION_TYPE_SET = 0x1,
6469 MLX5_ACTION_TYPE_ADD = 0x2,
6470 MLX5_ACTION_TYPE_COPY = 0x3,
6474 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
6475 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
6476 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
6477 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
6478 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
6479 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
6480 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
6481 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
6482 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
6483 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
6484 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
6485 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
6486 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
6487 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
6488 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
6489 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
6490 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
6491 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
6492 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
6493 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
6494 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
6495 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
6496 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
6497 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6498 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
6499 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
6500 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
6501 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
6502 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
6503 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
6504 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
6505 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
6506 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
6507 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
6508 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
6509 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
6510 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
6511 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F,
6512 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70,
6516 u8 status[0x8];
6517 u8 reserved_at_8[0x18];
6519 u8 syndrome[0x20];
6521 u8 modify_header_id[0x20];
6523 u8 reserved_at_60[0x20];
6527 u8 opcode[0x10];
6528 u8 reserved_at_10[0x10];
6530 u8 reserved_at_20[0x10];
6531 u8 op_mod[0x10];
6533 u8 reserved_at_40[0x20];
6535 u8 table_type[0x8];
6536 u8 reserved_at_68[0x10];
6537 u8 num_of_actions[0x8];
6543 u8 status[0x8];
6544 u8 reserved_at_8[0x18];
6546 u8 syndrome[0x20];
6548 u8 reserved_at_40[0x40];
6552 u8 opcode[0x10];
6553 u8 reserved_at_10[0x10];
6555 u8 reserved_at_20[0x10];
6556 u8 op_mod[0x10];
6558 u8 modify_header_id[0x20];
6560 u8 reserved_at_60[0x20];
6564 u8 opcode[0x10];
6565 u8 uid[0x10];
6567 u8 reserved_at_20[0x10];
6568 u8 op_mod[0x10];
6570 u8 modify_header_id[0x20];
6572 u8 reserved_at_60[0xa0];
6576 u8 status[0x8];
6577 u8 reserved_at_8[0x18];
6579 u8 syndrome[0x20];
6581 u8 reserved_at_40[0x40];
6585 u8 reserved_at_280[0x180];
6589 u8 opcode[0x10];
6590 u8 reserved_at_10[0x10];
6592 u8 reserved_at_20[0x10];
6593 u8 op_mod[0x10];
6595 u8 reserved_at_40[0x8];
6596 u8 dctn[0x18];
6598 u8 reserved_at_60[0x20];
6602 u8 status[0x8];
6603 u8 reserved_at_8[0x18];
6605 u8 syndrome[0x20];
6607 u8 reserved_at_40[0x40];
6611 u8 reserved_at_280[0x600];
6613 u8 pas[][0x40];
6617 u8 opcode[0x10];
6618 u8 reserved_at_10[0x10];
6620 u8 reserved_at_20[0x10];
6621 u8 op_mod[0x10];
6623 u8 reserved_at_40[0x8];
6624 u8 cqn[0x18];
6626 u8 reserved_at_60[0x20];
6630 u8 status[0x8];
6631 u8 reserved_at_8[0x18];
6633 u8 syndrome[0x20];
6635 u8 reserved_at_40[0x20];
6637 u8 enable[0x1];
6638 u8 tag_enable[0x1];
6639 u8 reserved_at_62[0x1e];
6643 u8 opcode[0x10];
6644 u8 reserved_at_10[0x10];
6646 u8 reserved_at_20[0x10];
6647 u8 op_mod[0x10];
6649 u8 reserved_at_40[0x18];
6650 u8 priority[0x4];
6651 u8 cong_protocol[0x4];
6653 u8 reserved_at_60[0x20];
6657 u8 status[0x8];
6658 u8 reserved_at_8[0x18];
6660 u8 syndrome[0x20];
6662 u8 reserved_at_40[0x40];
6664 u8 rp_cur_flows[0x20];
6666 u8 sum_flows[0x20];
6668 u8 rp_cnp_ignored_high[0x20];
6670 u8 rp_cnp_ignored_low[0x20];
6672 u8 rp_cnp_handled_high[0x20];
6674 u8 rp_cnp_handled_low[0x20];
6676 u8 reserved_at_140[0x100];
6678 u8 time_stamp_high[0x20];
6680 u8 time_stamp_low[0x20];
6682 u8 accumulators_period[0x20];
6684 u8 np_ecn_marked_roce_packets_high[0x20];
6686 u8 np_ecn_marked_roce_packets_low[0x20];
6688 u8 np_cnp_sent_high[0x20];
6690 u8 np_cnp_sent_low[0x20];
6692 u8 reserved_at_320[0x560];
6696 u8 opcode[0x10];
6697 u8 reserved_at_10[0x10];
6699 u8 reserved_at_20[0x10];
6700 u8 op_mod[0x10];
6702 u8 clear[0x1];
6703 u8 reserved_at_41[0x1f];
6705 u8 reserved_at_60[0x20];
6709 u8 status[0x8];
6710 u8 reserved_at_8[0x18];
6712 u8 syndrome[0x20];
6714 u8 reserved_at_40[0x40];
6720 u8 opcode[0x10];
6721 u8 reserved_at_10[0x10];
6723 u8 reserved_at_20[0x10];
6724 u8 op_mod[0x10];
6726 u8 reserved_at_40[0x1c];
6727 u8 cong_protocol[0x4];
6729 u8 reserved_at_60[0x20];
6733 u8 status[0x8];
6734 u8 reserved_at_8[0x18];
6736 u8 syndrome[0x20];
6738 u8 reserved_at_40[0x40];
6744 u8 opcode[0x10];
6745 u8 reserved_at_10[0x10];
6747 u8 reserved_at_20[0x10];
6748 u8 op_mod[0x10];
6750 u8 reserved_at_40[0x40];
6754 u8 status[0x8];
6755 u8 reserved_at_8[0x18];
6757 u8 syndrome[0x20];
6759 u8 reserved_at_40[0x40];
6763 u8 opcode[0x10];
6764 u8 uid[0x10];
6766 u8 reserved_at_20[0x10];
6767 u8 op_mod[0x10];
6769 u8 reserved_at_40[0x8];
6770 u8 qpn[0x18];
6772 u8 reserved_at_60[0x20];
6776 u8 status[0x8];
6777 u8 reserved_at_8[0x18];
6779 u8 syndrome[0x20];
6781 u8 reserved_at_40[0x40];
6785 u8 opcode[0x10];
6786 u8 uid[0x10];
6788 u8 reserved_at_20[0x10];
6789 u8 op_mod[0x10];
6791 u8 reserved_at_40[0x8];
6792 u8 qpn[0x18];
6794 u8 reserved_at_60[0x20];
6798 u8 status[0x8];
6799 u8 reserved_at_8[0x18];
6801 u8 syndrome[0x20];
6803 u8 reserved_at_40[0x40];
6807 u8 opcode[0x10];
6808 u8 reserved_at_10[0x10];
6810 u8 reserved_at_20[0x10];
6811 u8 op_mod[0x10];
6813 u8 error[0x1];
6814 u8 reserved_at_41[0x4];
6815 u8 page_fault_type[0x3];
6816 u8 wq_number[0x18];
6818 u8 reserved_at_60[0x8];
6819 u8 token[0x18];
6823 u8 status[0x8];
6824 u8 reserved_at_8[0x18];
6826 u8 syndrome[0x20];
6828 u8 reserved_at_40[0x40];
6832 u8 opcode[0x10];
6833 u8 reserved_at_10[0x10];
6835 u8 reserved_at_20[0x10];
6836 u8 op_mod[0x10];
6838 u8 reserved_at_40[0x40];
6842 u8 status[0x8];
6843 u8 reserved_at_8[0x18];
6845 u8 syndrome[0x20];
6847 u8 reserved_at_40[0x40];
6851 u8 opcode[0x10];
6852 u8 reserved_at_10[0x10];
6854 u8 reserved_at_20[0x10];
6855 u8 op_mod[0x10];
6857 u8 other_vport[0x1];
6858 u8 reserved_at_41[0xf];
6859 u8 vport_number[0x10];
6861 u8 reserved_at_60[0x18];
6862 u8 admin_state[0x4];
6863 u8 reserved_at_7c[0x4];
6867 u8 status[0x8];
6868 u8 reserved_at_8[0x18];
6870 u8 syndrome[0x20];
6872 u8 reserved_at_40[0x40];
6876 u8 reserved_at_0[0x20];
6878 u8 reserved_at_20[0x1d];
6879 u8 lag_tx_port_affinity[0x1];
6880 u8 strict_lag_tx_port_affinity[0x1];
6881 u8 prio[0x1];
6885 u8 opcode[0x10];
6886 u8 uid[0x10];
6888 u8 reserved_at_20[0x10];
6889 u8 op_mod[0x10];
6891 u8 reserved_at_40[0x8];
6892 u8 tisn[0x18];
6894 u8 reserved_at_60[0x20];
6898 u8 reserved_at_c0[0x40];
6904 u8 reserved_at_0[0x20];
6906 u8 reserved_at_20[0x1b];
6907 u8 self_lb_en[0x1];
6908 u8 reserved_at_3c[0x1];
6909 u8 hash[0x1];
6910 u8 reserved_at_3e[0x1];
6911 u8 packet_merge[0x1];
6915 u8 status[0x8];
6916 u8 reserved_at_8[0x18];
6918 u8 syndrome[0x20];
6920 u8 reserved_at_40[0x40];
6924 u8 opcode[0x10];
6925 u8 uid[0x10];
6927 u8 reserved_at_20[0x10];
6928 u8 op_mod[0x10];
6930 u8 reserved_at_40[0x8];
6931 u8 tirn[0x18];
6933 u8 reserved_at_60[0x20];
6937 u8 reserved_at_c0[0x40];
6943 u8 status[0x8];
6944 u8 reserved_at_8[0x18];
6946 u8 syndrome[0x20];
6948 u8 reserved_at_40[0x40];
6952 u8 opcode[0x10];
6953 u8 uid[0x10];
6955 u8 reserved_at_20[0x10];
6956 u8 op_mod[0x10];
6958 u8 sq_state[0x4];
6959 u8 reserved_at_44[0x4];
6960 u8 sqn[0x18];
6962 u8 reserved_at_60[0x20];
6964 u8 modify_bitmask[0x40];
6966 u8 reserved_at_c0[0x40];
6972 u8 status[0x8];
6973 u8 reserved_at_8[0x18];
6975 u8 syndrome[0x20];
6977 u8 reserved_at_40[0x1c0];
6981 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6982 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6986 u8 opcode[0x10];
6987 u8 reserved_at_10[0x10];
6989 u8 reserved_at_20[0x10];
6990 u8 op_mod[0x10];
6992 u8 scheduling_hierarchy[0x8];
6993 u8 reserved_at_48[0x18];
6995 u8 scheduling_element_id[0x20];
6997 u8 reserved_at_80[0x20];
6999 u8 modify_bitmask[0x20];
7001 u8 reserved_at_c0[0x40];
7005 u8 reserved_at_300[0x100];
7009 u8 status[0x8];
7010 u8 reserved_at_8[0x18];
7012 u8 syndrome[0x20];
7014 u8 reserved_at_40[0x40];
7018 u8 reserved_at_0[0x20];
7020 u8 reserved_at_20[0x1f];
7021 u8 rqn_list[0x1];
7025 u8 opcode[0x10];
7026 u8 uid[0x10];
7028 u8 reserved_at_20[0x10];
7029 u8 op_mod[0x10];
7031 u8 reserved_at_40[0x8];
7032 u8 rqtn[0x18];
7034 u8 reserved_at_60[0x20];
7038 u8 reserved_at_c0[0x40];
7044 u8 status[0x8];
7045 u8 reserved_at_8[0x18];
7047 u8 syndrome[0x20];
7049 u8 reserved_at_40[0x40];
7059 u8 opcode[0x10];
7060 u8 uid[0x10];
7062 u8 reserved_at_20[0x10];
7063 u8 op_mod[0x10];
7065 u8 rq_state[0x4];
7066 u8 reserved_at_44[0x4];
7067 u8 rqn[0x18];
7069 u8 reserved_at_60[0x20];
7071 u8 modify_bitmask[0x40];
7073 u8 reserved_at_c0[0x40];
7079 u8 status[0x8];
7080 u8 reserved_at_8[0x18];
7082 u8 syndrome[0x20];
7084 u8 reserved_at_40[0x40];
7088 u8 reserved_at_0[0x20];
7090 u8 reserved_at_20[0x1f];
7091 u8 lwm[0x1];
7095 u8 opcode[0x10];
7096 u8 uid[0x10];
7098 u8 reserved_at_20[0x10];
7099 u8 op_mod[0x10];
7101 u8 rmp_state[0x4];
7102 u8 reserved_at_44[0x4];
7103 u8 rmpn[0x18];
7105 u8 reserved_at_60[0x20];
7109 u8 reserved_at_c0[0x40];
7115 u8 status[0x8];
7116 u8 reserved_at_8[0x18];
7118 u8 syndrome[0x20];
7120 u8 reserved_at_40[0x40];
7124 u8 reserved_at_0[0x12];
7125 u8 affiliation[0x1];
7126 u8 reserved_at_13[0x1];
7127 u8 disable_uc_local_lb[0x1];
7128 u8 disable_mc_local_lb[0x1];
7129 u8 node_guid[0x1];
7130 u8 port_guid[0x1];
7131 u8 min_inline[0x1];
7132 u8 mtu[0x1];
7133 u8 change_event[0x1];
7134 u8 promisc[0x1];
7135 u8 permanent_address[0x1];
7136 u8 addresses_list[0x1];
7137 u8 roce_en[0x1];
7138 u8 reserved_at_1f[0x1];
7142 u8 opcode[0x10];
7143 u8 reserved_at_10[0x10];
7145 u8 reserved_at_20[0x10];
7146 u8 op_mod[0x10];
7148 u8 other_vport[0x1];
7149 u8 reserved_at_41[0xf];
7150 u8 vport_number[0x10];
7154 u8 reserved_at_80[0x780];
7160 u8 status[0x8];
7161 u8 reserved_at_8[0x18];
7163 u8 syndrome[0x20];
7165 u8 reserved_at_40[0x40];
7169 u8 opcode[0x10];
7170 u8 reserved_at_10[0x10];
7172 u8 reserved_at_20[0x10];
7173 u8 op_mod[0x10];
7175 u8 other_vport[0x1];
7176 u8 reserved_at_41[0xb];
7177 u8 port_num[0x4];
7178 u8 vport_number[0x10];
7180 u8 reserved_at_60[0x20];
7186 u8 status[0x8];
7187 u8 reserved_at_8[0x18];
7189 u8 syndrome[0x20];
7191 u8 reserved_at_40[0x40];
7195 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
7196 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
7200 u8 opcode[0x10];
7201 u8 uid[0x10];
7203 u8 reserved_at_20[0x10];
7204 u8 op_mod[0x10];
7206 u8 reserved_at_40[0x8];
7207 u8 cqn[0x18];
7213 u8 reserved_at_280[0x60];
7215 u8 cq_umem_valid[0x1];
7216 u8 reserved_at_2e1[0x1f];
7218 u8 reserved_at_300[0x580];
7220 u8 pas[][0x40];
7224 u8 status[0x8];
7225 u8 reserved_at_8[0x18];
7227 u8 syndrome[0x20];
7229 u8 reserved_at_40[0x40];
7233 u8 opcode[0x10];
7234 u8 reserved_at_10[0x10];
7236 u8 reserved_at_20[0x10];
7237 u8 op_mod[0x10];
7239 u8 reserved_at_40[0x18];
7240 u8 priority[0x4];
7241 u8 cong_protocol[0x4];
7243 u8 enable[0x1];
7244 u8 tag_enable[0x1];
7245 u8 reserved_at_62[0x1e];
7249 u8 status[0x8];
7250 u8 reserved_at_8[0x18];
7252 u8 syndrome[0x20];
7254 u8 reserved_at_40[0x40];
7258 u8 opcode[0x10];
7259 u8 reserved_at_10[0x10];
7261 u8 reserved_at_20[0x10];
7262 u8 op_mod[0x10];
7264 u8 reserved_at_40[0x1c];
7265 u8 cong_protocol[0x4];
7269 u8 reserved_at_80[0x80];
7275 u8 status[0x8];
7276 u8 reserved_at_8[0x18];
7278 u8 syndrome[0x20];
7280 u8 output_num_entries[0x20];
7282 u8 reserved_at_60[0x20];
7284 u8 pas[][0x40];
7288 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
7289 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
7290 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
7294 u8 opcode[0x10];
7295 u8 reserved_at_10[0x10];
7297 u8 reserved_at_20[0x10];
7298 u8 op_mod[0x10];
7300 u8 embedded_cpu_function[0x1];
7301 u8 reserved_at_41[0xf];
7302 u8 function_id[0x10];
7304 u8 input_num_entries[0x20];
7306 u8 pas[][0x40];
7310 u8 status[0x8];
7311 u8 reserved_at_8[0x18];
7313 u8 syndrome[0x20];
7315 u8 reserved_at_40[0x40];
7317 u8 response_mad_packet[256][0x8];
7321 u8 opcode[0x10];
7322 u8 reserved_at_10[0x10];
7324 u8 reserved_at_20[0x10];
7325 u8 op_mod[0x10];
7327 u8 remote_lid[0x10];
7328 u8 reserved_at_50[0x8];
7329 u8 port[0x8];
7331 u8 reserved_at_60[0x20];
7333 u8 mad[256][0x8];
7337 u8 status[0x8];
7338 u8 reserved_at_8[0x18];
7340 u8 syndrome[0x20];
7342 u8 reserved_at_40[0x40];
7346 u8 opcode[0x10];
7347 u8 reserved_at_10[0x10];
7349 u8 reserved_at_20[0x10];
7350 u8 op_mod[0x10];
7352 u8 reserved_at_40[0x20];
7354 u8 reserved_at_60[0x2];
7355 u8 sw_vhca_id[0xe];
7356 u8 reserved_at_70[0x10];
7358 u8 sw_owner_id[4][0x20];
7362 u8 status[0x8];
7363 u8 reserved_at_8[0x18];
7365 u8 syndrome[0x20];
7367 u8 reserved_at_40[0x20];
7368 u8 ece[0x20];
7372 u8 opcode[0x10];
7373 u8 uid[0x10];
7375 u8 reserved_at_20[0x10];
7376 u8 op_mod[0x10];
7378 u8 reserved_at_40[0x8];
7379 u8 qpn[0x18];
7381 u8 reserved_at_60[0x20];
7383 u8 opt_param_mask[0x20];
7385 u8 ece[0x20];
7389 u8 reserved_at_800[0x80];
7393 u8 status[0x8];
7394 u8 reserved_at_8[0x18];
7396 u8 syndrome[0x20];
7398 u8 reserved_at_40[0x20];
7399 u8 ece[0x20];
7403 u8 opcode[0x10];
7404 u8 uid[0x10];
7406 u8 reserved_at_20[0x10];
7407 u8 op_mod[0x10];
7409 u8 reserved_at_40[0x8];
7410 u8 qpn[0x18];
7412 u8 reserved_at_60[0x20];
7414 u8 opt_param_mask[0x20];
7416 u8 ece[0x20];
7420 u8 reserved_at_800[0x80];
7424 u8 status[0x8];
7425 u8 reserved_at_8[0x18];
7427 u8 syndrome[0x20];
7429 u8 reserved_at_40[0x40];
7431 u8 packet_headers_log[128][0x8];
7433 u8 packet_syndrome[64][0x8];
7437 u8 opcode[0x10];
7438 u8 reserved_at_10[0x10];
7440 u8 reserved_at_20[0x10];
7441 u8 op_mod[0x10];
7443 u8 reserved_at_40[0x40];
7447 u8 opcode[0x10];
7448 u8 reserved_at_10[0x10];
7450 u8 reserved_at_20[0x10];
7451 u8 op_mod[0x10];
7453 u8 reserved_at_40[0x18];
7454 u8 eq_number[0x8];
7456 u8 reserved_at_60[0x20];
7458 u8 eqe[64][0x8];
7462 u8 status[0x8];
7463 u8 reserved_at_8[0x18];
7465 u8 syndrome[0x20];
7467 u8 reserved_at_40[0x40];
7471 u8 status[0x8];
7472 u8 reserved_at_8[0x18];
7474 u8 syndrome[0x20];
7476 u8 reserved_at_40[0x20];
7480 u8 opcode[0x10];
7481 u8 reserved_at_10[0x10];
7483 u8 reserved_at_20[0x10];
7484 u8 op_mod[0x10];
7486 u8 embedded_cpu_function[0x1];
7487 u8 reserved_at_41[0xf];
7488 u8 function_id[0x10];
7490 u8 reserved_at_60[0x20];
7494 u8 status[0x8];
7495 u8 reserved_at_8[0x18];
7497 u8 syndrome[0x20];
7499 u8 reserved_at_40[0x40];
7503 u8 opcode[0x10];
7504 u8 uid[0x10];
7506 u8 reserved_at_20[0x10];
7507 u8 op_mod[0x10];
7509 u8 reserved_at_40[0x8];
7510 u8 dctn[0x18];
7512 u8 reserved_at_60[0x20];
7516 u8 status[0x8];
7517 u8 reserved_at_8[0x18];
7519 u8 syndrome[0x20];
7521 u8 reserved_at_40[0x20];
7525 u8 opcode[0x10];
7526 u8 reserved_at_10[0x10];
7528 u8 reserved_at_20[0x10];
7529 u8 op_mod[0x10];
7531 u8 embedded_cpu_function[0x1];
7532 u8 reserved_at_41[0xf];
7533 u8 function_id[0x10];
7535 u8 reserved_at_60[0x20];
7539 u8 status[0x8];
7540 u8 reserved_at_8[0x18];
7542 u8 syndrome[0x20];
7544 u8 reserved_at_40[0x40];
7548 u8 opcode[0x10];
7549 u8 uid[0x10];
7551 u8 reserved_at_20[0x10];
7552 u8 op_mod[0x10];
7554 u8 reserved_at_40[0x8];
7555 u8 qpn[0x18];
7557 u8 reserved_at_60[0x20];
7559 u8 multicast_gid[16][0x8];
7563 u8 status[0x8];
7564 u8 reserved_at_8[0x18];
7566 u8 syndrome[0x20];
7568 u8 reserved_at_40[0x40];
7572 u8 opcode[0x10];
7573 u8 uid[0x10];
7575 u8 reserved_at_20[0x10];
7576 u8 op_mod[0x10];
7578 u8 reserved_at_40[0x8];
7579 u8 xrqn[0x18];
7581 u8 reserved_at_60[0x20];
7585 u8 status[0x8];
7586 u8 reserved_at_8[0x18];
7588 u8 syndrome[0x20];
7590 u8 reserved_at_40[0x40];
7594 u8 opcode[0x10];
7595 u8 uid[0x10];
7597 u8 reserved_at_20[0x10];
7598 u8 op_mod[0x10];
7600 u8 reserved_at_40[0x8];
7601 u8 xrc_srqn[0x18];
7603 u8 reserved_at_60[0x20];
7607 u8 status[0x8];
7608 u8 reserved_at_8[0x18];
7610 u8 syndrome[0x20];
7612 u8 reserved_at_40[0x40];
7616 u8 opcode[0x10];
7617 u8 uid[0x10];
7619 u8 reserved_at_20[0x10];
7620 u8 op_mod[0x10];
7622 u8 reserved_at_40[0x8];
7623 u8 tisn[0x18];
7625 u8 reserved_at_60[0x20];
7629 u8 status[0x8];
7630 u8 reserved_at_8[0x18];
7632 u8 syndrome[0x20];
7634 u8 reserved_at_40[0x40];
7638 u8 opcode[0x10];
7639 u8 uid[0x10];
7641 u8 reserved_at_20[0x10];
7642 u8 op_mod[0x10];
7644 u8 reserved_at_40[0x8];
7645 u8 tirn[0x18];
7647 u8 reserved_at_60[0x20];
7651 u8 status[0x8];
7652 u8 reserved_at_8[0x18];
7654 u8 syndrome[0x20];
7656 u8 reserved_at_40[0x40];
7660 u8 opcode[0x10];
7661 u8 uid[0x10];
7663 u8 reserved_at_20[0x10];
7664 u8 op_mod[0x10];
7666 u8 reserved_at_40[0x8];
7667 u8 srqn[0x18];
7669 u8 reserved_at_60[0x20];
7673 u8 status[0x8];
7674 u8 reserved_at_8[0x18];
7676 u8 syndrome[0x20];
7678 u8 reserved_at_40[0x40];
7682 u8 opcode[0x10];
7683 u8 uid[0x10];
7685 u8 reserved_at_20[0x10];
7686 u8 op_mod[0x10];
7688 u8 reserved_at_40[0x8];
7689 u8 sqn[0x18];
7691 u8 reserved_at_60[0x20];
7695 u8 status[0x8];
7696 u8 reserved_at_8[0x18];
7698 u8 syndrome[0x20];
7700 u8 reserved_at_40[0x1c0];
7704 u8 opcode[0x10];
7705 u8 reserved_at_10[0x10];
7707 u8 reserved_at_20[0x10];
7708 u8 op_mod[0x10];
7710 u8 scheduling_hierarchy[0x8];
7711 u8 reserved_at_48[0x18];
7713 u8 scheduling_element_id[0x20];
7715 u8 reserved_at_80[0x180];
7719 u8 status[0x8];
7720 u8 reserved_at_8[0x18];
7722 u8 syndrome[0x20];
7724 u8 reserved_at_40[0x40];
7728 u8 opcode[0x10];
7729 u8 uid[0x10];
7731 u8 reserved_at_20[0x10];
7732 u8 op_mod[0x10];
7734 u8 reserved_at_40[0x8];
7735 u8 rqtn[0x18];
7737 u8 reserved_at_60[0x20];
7741 u8 status[0x8];
7742 u8 reserved_at_8[0x18];
7744 u8 syndrome[0x20];
7746 u8 reserved_at_40[0x40];
7750 u8 opcode[0x10];
7751 u8 uid[0x10];
7753 u8 reserved_at_20[0x10];
7754 u8 op_mod[0x10];
7756 u8 reserved_at_40[0x8];
7757 u8 rqn[0x18];
7759 u8 reserved_at_60[0x20];
7763 u8 opcode[0x10];
7764 u8 reserved_at_10[0x10];
7766 u8 reserved_at_20[0x10];
7767 u8 op_mod[0x10];
7769 u8 reserved_at_40[0x20];
7771 u8 reserved_at_60[0x10];
7772 u8 delay_drop_timeout[0x10];
7776 u8 status[0x8];
7777 u8 reserved_at_8[0x18];
7779 u8 syndrome[0x20];
7781 u8 reserved_at_40[0x40];
7785 u8 status[0x8];
7786 u8 reserved_at_8[0x18];
7788 u8 syndrome[0x20];
7790 u8 reserved_at_40[0x40];
7794 u8 opcode[0x10];
7795 u8 uid[0x10];
7797 u8 reserved_at_20[0x10];
7798 u8 op_mod[0x10];
7800 u8 reserved_at_40[0x8];
7801 u8 rmpn[0x18];
7803 u8 reserved_at_60[0x20];
7807 u8 status[0x8];
7808 u8 reserved_at_8[0x18];
7810 u8 syndrome[0x20];
7812 u8 reserved_at_40[0x40];
7816 u8 opcode[0x10];
7817 u8 uid[0x10];
7819 u8 reserved_at_20[0x10];
7820 u8 op_mod[0x10];
7822 u8 reserved_at_40[0x8];
7823 u8 qpn[0x18];
7825 u8 reserved_at_60[0x20];
7829 u8 status[0x8];
7830 u8 reserved_at_8[0x18];
7832 u8 syndrome[0x20];
7834 u8 reserved_at_40[0x40];
7838 u8 opcode[0x10];
7839 u8 reserved_at_10[0x10];
7841 u8 reserved_at_20[0x10];
7842 u8 op_mod[0x10];
7844 u8 reserved_at_40[0x8];
7845 u8 psvn[0x18];
7847 u8 reserved_at_60[0x20];
7851 u8 status[0x8];
7852 u8 reserved_at_8[0x18];
7854 u8 syndrome[0x20];
7856 u8 reserved_at_40[0x40];
7860 u8 opcode[0x10];
7861 u8 uid[0x10];
7863 u8 reserved_at_20[0x10];
7864 u8 op_mod[0x10];
7866 u8 reserved_at_40[0x8];
7867 u8 mkey_index[0x18];
7869 u8 reserved_at_60[0x20];
7873 u8 status[0x8];
7874 u8 reserved_at_8[0x18];
7876 u8 syndrome[0x20];
7878 u8 reserved_at_40[0x40];
7882 u8 opcode[0x10];
7883 u8 reserved_at_10[0x10];
7885 u8 reserved_at_20[0x10];
7886 u8 op_mod[0x10];
7888 u8 other_vport[0x1];
7889 u8 reserved_at_41[0xf];
7890 u8 vport_number[0x10];
7892 u8 reserved_at_60[0x20];
7894 u8 table_type[0x8];
7895 u8 reserved_at_88[0x18];
7897 u8 reserved_at_a0[0x8];
7898 u8 table_id[0x18];
7900 u8 reserved_at_c0[0x140];
7904 u8 status[0x8];
7905 u8 reserved_at_8[0x18];
7907 u8 syndrome[0x20];
7909 u8 reserved_at_40[0x40];
7913 u8 opcode[0x10];
7914 u8 reserved_at_10[0x10];
7916 u8 reserved_at_20[0x10];
7917 u8 op_mod[0x10];
7919 u8 other_vport[0x1];
7920 u8 reserved_at_41[0xf];
7921 u8 vport_number[0x10];
7923 u8 reserved_at_60[0x20];
7925 u8 table_type[0x8];
7926 u8 reserved_at_88[0x18];
7928 u8 reserved_at_a0[0x8];
7929 u8 table_id[0x18];
7931 u8 group_id[0x20];
7933 u8 reserved_at_e0[0x120];
7937 u8 status[0x8];
7938 u8 reserved_at_8[0x18];
7940 u8 syndrome[0x20];
7942 u8 reserved_at_40[0x40];
7946 u8 opcode[0x10];
7947 u8 reserved_at_10[0x10];
7949 u8 reserved_at_20[0x10];
7950 u8 op_mod[0x10];
7952 u8 reserved_at_40[0x18];
7953 u8 eq_number[0x8];
7955 u8 reserved_at_60[0x20];
7959 u8 status[0x8];
7960 u8 reserved_at_8[0x18];
7962 u8 syndrome[0x20];
7964 u8 reserved_at_40[0x40];
7968 u8 opcode[0x10];
7969 u8 uid[0x10];
7971 u8 reserved_at_20[0x10];
7972 u8 op_mod[0x10];
7974 u8 reserved_at_40[0x8];
7975 u8 dctn[0x18];
7977 u8 reserved_at_60[0x20];
7981 u8 status[0x8];
7982 u8 reserved_at_8[0x18];
7984 u8 syndrome[0x20];
7986 u8 reserved_at_40[0x40];
7990 u8 opcode[0x10];
7991 u8 uid[0x10];
7993 u8 reserved_at_20[0x10];
7994 u8 op_mod[0x10];
7996 u8 reserved_at_40[0x8];
7997 u8 cqn[0x18];
7999 u8 reserved_at_60[0x20];
8003 u8 status[0x8];
8004 u8 reserved_at_8[0x18];
8006 u8 syndrome[0x20];
8008 u8 reserved_at_40[0x40];
8012 u8 opcode[0x10];
8013 u8 reserved_at_10[0x10];
8015 u8 reserved_at_20[0x10];
8016 u8 op_mod[0x10];
8018 u8 reserved_at_40[0x20];
8020 u8 reserved_at_60[0x10];
8021 u8 vxlan_udp_port[0x10];
8025 u8 status[0x8];
8026 u8 reserved_at_8[0x18];
8028 u8 syndrome[0x20];
8030 u8 reserved_at_40[0x40];
8034 u8 opcode[0x10];
8035 u8 reserved_at_10[0x10];
8037 u8 reserved_at_20[0x10];
8038 u8 op_mod[0x10];
8040 u8 reserved_at_40[0x60];
8042 u8 reserved_at_a0[0x8];
8043 u8 table_index[0x18];
8045 u8 reserved_at_c0[0x140];
8049 u8 status[0x8];
8050 u8 reserved_at_8[0x18];
8052 u8 syndrome[0x20];
8054 u8 reserved_at_40[0x40];
8058 u8 opcode[0x10];
8059 u8 reserved_at_10[0x10];
8061 u8 reserved_at_20[0x10];
8062 u8 op_mod[0x10];
8064 u8 other_vport[0x1];
8065 u8 reserved_at_41[0xf];
8066 u8 vport_number[0x10];
8068 u8 reserved_at_60[0x20];
8070 u8 table_type[0x8];
8071 u8 reserved_at_88[0x18];
8073 u8 reserved_at_a0[0x8];
8074 u8 table_id[0x18];
8076 u8 reserved_at_c0[0x40];
8078 u8 flow_index[0x20];
8080 u8 reserved_at_120[0xe0];
8084 u8 status[0x8];
8085 u8 reserved_at_8[0x18];
8087 u8 syndrome[0x20];
8089 u8 reserved_at_40[0x40];
8093 u8 opcode[0x10];
8094 u8 uid[0x10];
8096 u8 reserved_at_20[0x10];
8097 u8 op_mod[0x10];
8099 u8 reserved_at_40[0x8];
8100 u8 xrcd[0x18];
8102 u8 reserved_at_60[0x20];
8106 u8 status[0x8];
8107 u8 reserved_at_8[0x18];
8109 u8 syndrome[0x20];
8111 u8 reserved_at_40[0x40];
8115 u8 opcode[0x10];
8116 u8 uid[0x10];
8118 u8 reserved_at_20[0x10];
8119 u8 op_mod[0x10];
8121 u8 reserved_at_40[0x8];
8122 u8 uar[0x18];
8124 u8 reserved_at_60[0x20];
8128 u8 status[0x8];
8129 u8 reserved_at_8[0x18];
8131 u8 syndrome[0x20];
8133 u8 reserved_at_40[0x40];
8137 u8 opcode[0x10];
8138 u8 uid[0x10];
8140 u8 reserved_at_20[0x10];
8141 u8 op_mod[0x10];
8143 u8 reserved_at_40[0x8];
8144 u8 transport_domain[0x18];
8146 u8 reserved_at_60[0x20];
8150 u8 status[0x8];
8151 u8 reserved_at_8[0x18];
8153 u8 syndrome[0x20];
8155 u8 reserved_at_40[0x40];
8159 u8 opcode[0x10];
8160 u8 reserved_at_10[0x10];
8162 u8 reserved_at_20[0x10];
8163 u8 op_mod[0x10];
8165 u8 reserved_at_40[0x18];
8166 u8 counter_set_id[0x8];
8168 u8 reserved_at_60[0x20];
8172 u8 status[0x8];
8173 u8 reserved_at_8[0x18];
8175 u8 syndrome[0x20];
8177 u8 reserved_at_40[0x40];
8181 u8 opcode[0x10];
8182 u8 uid[0x10];
8184 u8 reserved_at_20[0x10];
8185 u8 op_mod[0x10];
8187 u8 reserved_at_40[0x8];
8188 u8 pd[0x18];
8190 u8 reserved_at_60[0x20];
8194 u8 status[0x8];
8195 u8 reserved_at_8[0x18];
8197 u8 syndrome[0x20];
8199 u8 reserved_at_40[0x40];
8203 u8 opcode[0x10];
8204 u8 reserved_at_10[0x10];
8206 u8 reserved_at_20[0x10];
8207 u8 op_mod[0x10];
8209 u8 flow_counter_id[0x20];
8211 u8 reserved_at_60[0x20];
8215 u8 status[0x8];
8216 u8 reserved_at_8[0x18];
8218 u8 syndrome[0x20];
8220 u8 reserved_at_40[0x8];
8221 u8 xrqn[0x18];
8223 u8 reserved_at_60[0x20];
8227 u8 opcode[0x10];
8228 u8 uid[0x10];
8230 u8 reserved_at_20[0x10];
8231 u8 op_mod[0x10];
8233 u8 reserved_at_40[0x40];
8239 u8 status[0x8];
8240 u8 reserved_at_8[0x18];
8242 u8 syndrome[0x20];
8244 u8 reserved_at_40[0x8];
8245 u8 xrc_srqn[0x18];
8247 u8 reserved_at_60[0x20];
8251 u8 opcode[0x10];
8252 u8 uid[0x10];
8254 u8 reserved_at_20[0x10];
8255 u8 op_mod[0x10];
8257 u8 reserved_at_40[0x40];
8261 u8 reserved_at_280[0x60];
8263 u8 xrc_srq_umem_valid[0x1];
8264 u8 reserved_at_2e1[0x1f];
8266 u8 reserved_at_300[0x580];
8268 u8 pas[][0x40];
8272 u8 status[0x8];
8273 u8 reserved_at_8[0x18];
8275 u8 syndrome[0x20];
8277 u8 reserved_at_40[0x8];
8278 u8 tisn[0x18];
8280 u8 reserved_at_60[0x20];
8284 u8 opcode[0x10];
8285 u8 uid[0x10];
8287 u8 reserved_at_20[0x10];
8288 u8 op_mod[0x10];
8290 u8 reserved_at_40[0xc0];
8296 u8 status[0x8];
8297 u8 icm_address_63_40[0x18];
8299 u8 syndrome[0x20];
8301 u8 icm_address_39_32[0x8];
8302 u8 tirn[0x18];
8304 u8 icm_address_31_0[0x20];
8308 u8 opcode[0x10];
8309 u8 uid[0x10];
8311 u8 reserved_at_20[0x10];
8312 u8 op_mod[0x10];
8314 u8 reserved_at_40[0xc0];
8320 u8 status[0x8];
8321 u8 reserved_at_8[0x18];
8323 u8 syndrome[0x20];
8325 u8 reserved_at_40[0x8];
8326 u8 srqn[0x18];
8328 u8 reserved_at_60[0x20];
8332 u8 opcode[0x10];
8333 u8 uid[0x10];
8335 u8 reserved_at_20[0x10];
8336 u8 op_mod[0x10];
8338 u8 reserved_at_40[0x40];
8342 u8 reserved_at_280[0x600];
8344 u8 pas[][0x40];
8348 u8 status[0x8];
8349 u8 reserved_at_8[0x18];
8351 u8 syndrome[0x20];
8353 u8 reserved_at_40[0x8];
8354 u8 sqn[0x18];
8356 u8 reserved_at_60[0x20];
8360 u8 opcode[0x10];
8361 u8 uid[0x10];
8363 u8 reserved_at_20[0x10];
8364 u8 op_mod[0x10];
8366 u8 reserved_at_40[0xc0];
8372 u8 status[0x8];
8373 u8 reserved_at_8[0x18];
8375 u8 syndrome[0x20];
8377 u8 reserved_at_40[0x40];
8379 u8 scheduling_element_id[0x20];
8381 u8 reserved_at_a0[0x160];
8385 u8 opcode[0x10];
8386 u8 reserved_at_10[0x10];
8388 u8 reserved_at_20[0x10];
8389 u8 op_mod[0x10];
8391 u8 scheduling_hierarchy[0x8];
8392 u8 reserved_at_48[0x18];
8394 u8 reserved_at_60[0xa0];
8398 u8 reserved_at_300[0x100];
8402 u8 status[0x8];
8403 u8 reserved_at_8[0x18];
8405 u8 syndrome[0x20];
8407 u8 reserved_at_40[0x8];
8408 u8 rqtn[0x18];
8410 u8 reserved_at_60[0x20];
8414 u8 opcode[0x10];
8415 u8 uid[0x10];
8417 u8 reserved_at_20[0x10];
8418 u8 op_mod[0x10];
8420 u8 reserved_at_40[0xc0];
8426 u8 status[0x8];
8427 u8 reserved_at_8[0x18];
8429 u8 syndrome[0x20];
8431 u8 reserved_at_40[0x8];
8432 u8 rqn[0x18];
8434 u8 reserved_at_60[0x20];
8438 u8 opcode[0x10];
8439 u8 uid[0x10];
8441 u8 reserved_at_20[0x10];
8442 u8 op_mod[0x10];
8444 u8 reserved_at_40[0xc0];
8450 u8 status[0x8];
8451 u8 reserved_at_8[0x18];
8453 u8 syndrome[0x20];
8455 u8 reserved_at_40[0x8];
8456 u8 rmpn[0x18];
8458 u8 reserved_at_60[0x20];
8462 u8 opcode[0x10];
8463 u8 uid[0x10];
8465 u8 reserved_at_20[0x10];
8466 u8 op_mod[0x10];
8468 u8 reserved_at_40[0xc0];
8474 u8 status[0x8];
8475 u8 reserved_at_8[0x18];
8477 u8 syndrome[0x20];
8479 u8 reserved_at_40[0x8];
8480 u8 qpn[0x18];
8482 u8 ece[0x20];
8486 u8 opcode[0x10];
8487 u8 uid[0x10];
8489 u8 reserved_at_20[0x10];
8490 u8 op_mod[0x10];
8492 u8 reserved_at_40[0x8];
8493 u8 input_qpn[0x18];
8495 u8 reserved_at_60[0x20];
8496 u8 opt_param_mask[0x20];
8498 u8 ece[0x20];
8502 u8 reserved_at_800[0x60];
8504 u8 wq_umem_valid[0x1];
8505 u8 reserved_at_861[0x1f];
8507 u8 pas[][0x40];
8511 u8 status[0x8];
8512 u8 reserved_at_8[0x18];
8514 u8 syndrome[0x20];
8516 u8 reserved_at_40[0x40];
8518 u8 reserved_at_80[0x8];
8519 u8 psv0_index[0x18];
8521 u8 reserved_at_a0[0x8];
8522 u8 psv1_index[0x18];
8524 u8 reserved_at_c0[0x8];
8525 u8 psv2_index[0x18];
8527 u8 reserved_at_e0[0x8];
8528 u8 psv3_index[0x18];
8532 u8 opcode[0x10];
8533 u8 reserved_at_10[0x10];
8535 u8 reserved_at_20[0x10];
8536 u8 op_mod[0x10];
8538 u8 num_psv[0x4];
8539 u8 reserved_at_44[0x4];
8540 u8 pd[0x18];
8542 u8 reserved_at_60[0x20];
8546 u8 status[0x8];
8547 u8 reserved_at_8[0x18];
8549 u8 syndrome[0x20];
8551 u8 reserved_at_40[0x8];
8552 u8 mkey_index[0x18];
8554 u8 reserved_at_60[0x20];
8558 u8 opcode[0x10];
8559 u8 uid[0x10];
8561 u8 reserved_at_20[0x10];
8562 u8 op_mod[0x10];
8564 u8 reserved_at_40[0x20];
8566 u8 pg_access[0x1];
8567 u8 mkey_umem_valid[0x1];
8568 u8 reserved_at_62[0x1e];
8572 u8 reserved_at_280[0x80];
8574 u8 translations_octword_actual_size[0x20];
8576 u8 reserved_at_320[0x560];
8578 u8 klm_pas_mtt[][0x20];
8582 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
8583 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
8584 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
8585 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
8586 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
8587 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
8588 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
8592 u8 status[0x8];
8593 u8 icm_address_63_40[0x18];
8595 u8 syndrome[0x20];
8597 u8 icm_address_39_32[0x8];
8598 u8 table_id[0x18];
8600 u8 icm_address_31_0[0x20];
8604 u8 opcode[0x10];
8605 u8 uid[0x10];
8607 u8 reserved_at_20[0x10];
8608 u8 op_mod[0x10];
8610 u8 other_vport[0x1];
8611 u8 reserved_at_41[0xf];
8612 u8 vport_number[0x10];
8614 u8 reserved_at_60[0x20];
8616 u8 table_type[0x8];
8617 u8 reserved_at_88[0x18];
8619 u8 reserved_at_a0[0x20];
8625 u8 status[0x8];
8626 u8 reserved_at_8[0x18];
8628 u8 syndrome[0x20];
8630 u8 reserved_at_40[0x8];
8631 u8 group_id[0x18];
8633 u8 reserved_at_60[0x20];
8637 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0,
8638 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1,
8642 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
8643 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
8644 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
8645 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8649 u8 opcode[0x10];
8650 u8 reserved_at_10[0x10];
8652 u8 reserved_at_20[0x10];
8653 u8 op_mod[0x10];
8655 u8 other_vport[0x1];
8656 u8 reserved_at_41[0xf];
8657 u8 vport_number[0x10];
8659 u8 reserved_at_60[0x20];
8661 u8 table_type[0x8];
8662 u8 reserved_at_88[0x4];
8663 u8 group_type[0x4];
8664 u8 reserved_at_90[0x10];
8666 u8 reserved_at_a0[0x8];
8667 u8 table_id[0x18];
8669 u8 source_eswitch_owner_vhca_id_valid[0x1];
8671 u8 reserved_at_c1[0x1f];
8673 u8 start_flow_index[0x20];
8675 u8 reserved_at_100[0x20];
8677 u8 end_flow_index[0x20];
8679 u8 reserved_at_140[0x10];
8680 u8 match_definer_id[0x10];
8682 u8 reserved_at_160[0x80];
8684 u8 reserved_at_1e0[0x18];
8685 u8 match_criteria_enable[0x8];
8689 u8 reserved_at_1200[0xe00];
8693 u8 status[0x8];
8694 u8 reserved_at_8[0x18];
8696 u8 syndrome[0x20];
8698 u8 reserved_at_40[0x18];
8699 u8 eq_number[0x8];
8701 u8 reserved_at_60[0x20];
8705 u8 opcode[0x10];
8706 u8 uid[0x10];
8708 u8 reserved_at_20[0x10];
8709 u8 op_mod[0x10];
8711 u8 reserved_at_40[0x40];
8715 u8 reserved_at_280[0x40];
8717 u8 event_bitmask[4][0x40];
8719 u8 reserved_at_3c0[0x4c0];
8721 u8 pas[][0x40];
8725 u8 status[0x8];
8726 u8 reserved_at_8[0x18];
8728 u8 syndrome[0x20];
8730 u8 reserved_at_40[0x8];
8731 u8 dctn[0x18];
8733 u8 ece[0x20];
8737 u8 opcode[0x10];
8738 u8 uid[0x10];
8740 u8 reserved_at_20[0x10];
8741 u8 op_mod[0x10];
8743 u8 reserved_at_40[0x40];
8747 u8 reserved_at_280[0x180];
8751 u8 status[0x8];
8752 u8 reserved_at_8[0x18];
8754 u8 syndrome[0x20];
8756 u8 reserved_at_40[0x8];
8757 u8 cqn[0x18];
8759 u8 reserved_at_60[0x20];
8763 u8 opcode[0x10];
8764 u8 uid[0x10];
8766 u8 reserved_at_20[0x10];
8767 u8 op_mod[0x10];
8769 u8 reserved_at_40[0x40];
8773 u8 reserved_at_280[0x60];
8775 u8 cq_umem_valid[0x1];
8776 u8 reserved_at_2e1[0x59f];
8778 u8 pas[][0x40];
8782 u8 status[0x8];
8783 u8 reserved_at_8[0x18];
8785 u8 syndrome[0x20];
8787 u8 reserved_at_40[0x4];
8788 u8 min_delay[0xc];
8789 u8 int_vector[0x10];
8791 u8 reserved_at_60[0x20];
8795 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8796 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8800 u8 opcode[0x10];
8801 u8 reserved_at_10[0x10];
8803 u8 reserved_at_20[0x10];
8804 u8 op_mod[0x10];
8806 u8 reserved_at_40[0x4];
8807 u8 min_delay[0xc];
8808 u8 int_vector[0x10];
8810 u8 reserved_at_60[0x20];
8814 u8 status[0x8];
8815 u8 reserved_at_8[0x18];
8817 u8 syndrome[0x20];
8819 u8 reserved_at_40[0x40];
8823 u8 opcode[0x10];
8824 u8 uid[0x10];
8826 u8 reserved_at_20[0x10];
8827 u8 op_mod[0x10];
8829 u8 reserved_at_40[0x8];
8830 u8 qpn[0x18];
8832 u8 reserved_at_60[0x20];
8834 u8 multicast_gid[16][0x8];
8838 u8 status[0x8];
8839 u8 reserved_at_8[0x18];
8841 u8 syndrome[0x20];
8843 u8 reserved_at_40[0x40];
8847 u8 opcode[0x10];
8848 u8 reserved_at_10[0x10];
8850 u8 reserved_at_20[0x10];
8851 u8 op_mod[0x10];
8853 u8 reserved_at_40[0x8];
8854 u8 xrqn[0x18];
8856 u8 reserved_at_60[0x10];
8857 u8 lwm[0x10];
8861 u8 status[0x8];
8862 u8 reserved_at_8[0x18];
8864 u8 syndrome[0x20];
8866 u8 reserved_at_40[0x40];
8870 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8874 u8 opcode[0x10];
8875 u8 uid[0x10];
8877 u8 reserved_at_20[0x10];
8878 u8 op_mod[0x10];
8880 u8 reserved_at_40[0x8];
8881 u8 xrc_srqn[0x18];
8883 u8 reserved_at_60[0x10];
8884 u8 lwm[0x10];
8888 u8 status[0x8];
8889 u8 reserved_at_8[0x18];
8891 u8 syndrome[0x20];
8893 u8 reserved_at_40[0x40];
8897 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8898 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8902 u8 opcode[0x10];
8903 u8 uid[0x10];
8905 u8 reserved_at_20[0x10];
8906 u8 op_mod[0x10];
8908 u8 reserved_at_40[0x8];
8909 u8 srq_number[0x18];
8911 u8 reserved_at_60[0x10];
8912 u8 lwm[0x10];
8916 u8 status[0x8];
8917 u8 reserved_at_8[0x18];
8919 u8 syndrome[0x20];
8921 u8 reserved_at_40[0x40];
8925 u8 opcode[0x10];
8926 u8 reserved_at_10[0x10];
8928 u8 reserved_at_20[0x10];
8929 u8 op_mod[0x10];
8931 u8 reserved_at_40[0x8];
8932 u8 dct_number[0x18];
8934 u8 reserved_at_60[0x20];
8938 u8 status[0x8];
8939 u8 reserved_at_8[0x18];
8941 u8 syndrome[0x20];
8943 u8 reserved_at_40[0x8];
8944 u8 xrcd[0x18];
8946 u8 reserved_at_60[0x20];
8950 u8 opcode[0x10];
8951 u8 uid[0x10];
8953 u8 reserved_at_20[0x10];
8954 u8 op_mod[0x10];
8956 u8 reserved_at_40[0x40];
8960 u8 status[0x8];
8961 u8 reserved_at_8[0x18];
8963 u8 syndrome[0x20];
8965 u8 reserved_at_40[0x8];
8966 u8 uar[0x18];
8968 u8 reserved_at_60[0x20];
8972 u8 opcode[0x10];
8973 u8 uid[0x10];
8975 u8 reserved_at_20[0x10];
8976 u8 op_mod[0x10];
8978 u8 reserved_at_40[0x40];
8982 u8 status[0x8];
8983 u8 reserved_at_8[0x18];
8985 u8 syndrome[0x20];
8987 u8 reserved_at_40[0x8];
8988 u8 transport_domain[0x18];
8990 u8 reserved_at_60[0x20];
8994 u8 opcode[0x10];
8995 u8 uid[0x10];
8997 u8 reserved_at_20[0x10];
8998 u8 op_mod[0x10];
9000 u8 reserved_at_40[0x40];
9004 u8 status[0x8];
9005 u8 reserved_at_8[0x18];
9007 u8 syndrome[0x20];
9009 u8 reserved_at_40[0x18];
9010 u8 counter_set_id[0x8];
9012 u8 reserved_at_60[0x20];
9016 u8 opcode[0x10];
9017 u8 uid[0x10];
9019 u8 reserved_at_20[0x10];
9020 u8 op_mod[0x10];
9022 u8 reserved_at_40[0x40];
9026 u8 status[0x8];
9027 u8 reserved_at_8[0x18];
9029 u8 syndrome[0x20];
9031 u8 reserved_at_40[0x8];
9032 u8 pd[0x18];
9034 u8 reserved_at_60[0x20];
9038 u8 opcode[0x10];
9039 u8 uid[0x10];
9041 u8 reserved_at_20[0x10];
9042 u8 op_mod[0x10];
9044 u8 reserved_at_40[0x40];
9048 u8 status[0x8];
9049 u8 reserved_at_8[0x18];
9051 u8 syndrome[0x20];
9053 u8 flow_counter_id[0x20];
9055 u8 reserved_at_60[0x20];
9059 u8 opcode[0x10];
9060 u8 reserved_at_10[0x10];
9062 u8 reserved_at_20[0x10];
9063 u8 op_mod[0x10];
9065 u8 reserved_at_40[0x38];
9066 u8 flow_counter_bulk[0x8];
9070 u8 status[0x8];
9071 u8 reserved_at_8[0x18];
9073 u8 syndrome[0x20];
9075 u8 reserved_at_40[0x40];
9079 u8 opcode[0x10];
9080 u8 reserved_at_10[0x10];
9082 u8 reserved_at_20[0x10];
9083 u8 op_mod[0x10];
9085 u8 reserved_at_40[0x20];
9087 u8 reserved_at_60[0x10];
9088 u8 vxlan_udp_port[0x10];
9092 u8 status[0x8];
9093 u8 reserved_at_8[0x18];
9095 u8 syndrome[0x20];
9097 u8 reserved_at_40[0x40];
9101 u8 rate_limit[0x20];
9103 u8 burst_upper_bound[0x20];
9105 u8 reserved_at_40[0x10];
9106 u8 typical_packet_size[0x10];
9108 u8 reserved_at_60[0x120];
9112 u8 opcode[0x10];
9113 u8 uid[0x10];
9115 u8 reserved_at_20[0x10];
9116 u8 op_mod[0x10];
9118 u8 reserved_at_40[0x10];
9119 u8 rate_limit_index[0x10];
9121 u8 reserved_at_60[0x20];
9127 u8 status[0x8];
9128 u8 reserved_at_8[0x18];
9130 u8 syndrome[0x20];
9132 u8 reserved_at_40[0x40];
9134 u8 register_data[][0x20];
9138 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
9139 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
9143 u8 opcode[0x10];
9144 u8 reserved_at_10[0x10];
9146 u8 reserved_at_20[0x10];
9147 u8 op_mod[0x10];
9149 u8 reserved_at_40[0x10];
9150 u8 register_id[0x10];
9152 u8 argument[0x20];
9154 u8 register_data[][0x20];
9158 u8 status[0x4];
9159 u8 version[0x4];
9160 u8 local_port[0x8];
9161 u8 pnat[0x2];
9162 u8 reserved_at_12[0x2];
9163 u8 lane[0x4];
9164 u8 reserved_at_18[0x8];
9166 u8 reserved_at_20[0x20];
9168 u8 reserved_at_40[0x7];
9169 u8 polarity[0x1];
9170 u8 ob_tap0[0x8];
9171 u8 ob_tap1[0x8];
9172 u8 ob_tap2[0x8];
9174 u8 reserved_at_60[0xc];
9175 u8 ob_preemp_mode[0x4];
9176 u8 ob_reg[0x8];
9177 u8 ob_bias[0x8];
9179 u8 reserved_at_80[0x20];
9183 u8 status[0x4];
9184 u8 version[0x4];
9185 u8 local_port[0x8];
9186 u8 pnat[0x2];
9187 u8 reserved_at_12[0x2];
9188 u8 lane[0x4];
9189 u8 reserved_at_18[0x8];
9191 u8 time_to_link_up[0x10];
9192 u8 reserved_at_30[0xc];
9193 u8 grade_lane_speed[0x4];
9195 u8 grade_version[0x8];
9196 u8 grade[0x18];
9198 u8 reserved_at_60[0x4];
9199 u8 height_grade_type[0x4];
9200 u8 height_grade[0x18];
9202 u8 height_dz[0x10];
9203 u8 height_dv[0x10];
9205 u8 reserved_at_a0[0x10];
9206 u8 height_sigma[0x10];
9208 u8 reserved_at_c0[0x20];
9210 u8 reserved_at_e0[0x4];
9211 u8 phase_grade_type[0x4];
9212 u8 phase_grade[0x18];
9214 u8 reserved_at_100[0x8];
9215 u8 phase_eo_pos[0x8];
9216 u8 reserved_at_110[0x8];
9217 u8 phase_eo_neg[0x8];
9219 u8 ffe_set_tested[0x10];
9220 u8 test_errors_per_lane[0x10];
9224 u8 reserved_at_0[0x8];
9225 u8 local_port[0x8];
9226 u8 reserved_at_10[0x10];
9228 u8 reserved_at_20[0x1c];
9229 u8 vl_hw_cap[0x4];
9231 u8 reserved_at_40[0x1c];
9232 u8 vl_admin[0x4];
9234 u8 reserved_at_60[0x1c];
9235 u8 vl_operational[0x4];
9239 u8 swid[0x8];
9240 u8 local_port[0x8];
9241 u8 reserved_at_10[0x4];
9242 u8 admin_status[0x4];
9243 u8 reserved_at_18[0x4];
9244 u8 oper_status[0x4];
9246 u8 reserved_at_20[0x60];
9250 u8 reserved_at_0[0x1];
9251 u8 an_disable_admin[0x1];
9252 u8 an_disable_cap[0x1];
9253 u8 reserved_at_3[0x5];
9254 u8 local_port[0x8];
9255 u8 reserved_at_10[0xd];
9256 u8 proto_mask[0x3];
9258 u8 an_status[0x4];
9259 u8 reserved_at_24[0xc];
9260 u8 data_rate_oper[0x10];
9262 u8 ext_eth_proto_capability[0x20];
9264 u8 eth_proto_capability[0x20];
9266 u8 ib_link_width_capability[0x10];
9267 u8 ib_proto_capability[0x10];
9269 u8 ext_eth_proto_admin[0x20];
9271 u8 eth_proto_admin[0x20];
9273 u8 ib_link_width_admin[0x10];
9274 u8 ib_proto_admin[0x10];
9276 u8 ext_eth_proto_oper[0x20];
9278 u8 eth_proto_oper[0x20];
9280 u8 ib_link_width_oper[0x10];
9281 u8 ib_proto_oper[0x10];
9283 u8 reserved_at_160[0x1c];
9284 u8 connector_type[0x4];
9286 u8 eth_proto_lp_advertise[0x20];
9288 u8 reserved_at_1a0[0x60];
9292 u8 reserved_at_0[0x8];
9293 u8 local_port[0x8];
9294 u8 reserved_at_10[0x20];
9296 u8 beacon_duration[0x10];
9297 u8 reserved_at_40[0x10];
9299 u8 beacon_remain[0x10];
9303 u8 reserved_at_0[0x20];
9305 u8 algorithm_options[0x10];
9306 u8 reserved_at_30[0x4];
9307 u8 repetitions_mode[0x4];
9308 u8 num_of_repetitions[0x8];
9310 u8 grade_version[0x8];
9311 u8 height_grade_type[0x4];
9312 u8 phase_grade_type[0x4];
9313 u8 height_grade_weight[0x8];
9314 u8 phase_grade_weight[0x8];
9316 u8 gisim_measure_bits[0x10];
9317 u8 adaptive_tap_measure_bits[0x10];
9319 u8 ber_bath_high_error_threshold[0x10];
9320 u8 ber_bath_mid_error_threshold[0x10];
9322 u8 ber_bath_low_error_threshold[0x10];
9323 u8 one_ratio_high_threshold[0x10];
9325 u8 one_ratio_high_mid_threshold[0x10];
9326 u8 one_ratio_low_mid_threshold[0x10];
9328 u8 one_ratio_low_threshold[0x10];
9329 u8 ndeo_error_threshold[0x10];
9331 u8 mixer_offset_step_size[0x10];
9332 u8 reserved_at_110[0x8];
9333 u8 mix90_phase_for_voltage_bath[0x8];
9335 u8 mixer_offset_start[0x10];
9336 u8 mixer_offset_end[0x10];
9338 u8 reserved_at_140[0x15];
9339 u8 ber_test_time[0xb];
9343 u8 swid[0x8];
9344 u8 local_port[0x8];
9345 u8 sub_port[0x8];
9346 u8 reserved_at_18[0x8];
9348 u8 reserved_at_20[0x20];
9352 u8 reserved_at_0[0x8];
9353 u8 local_port[0x8];
9354 u8 reserved_at_10[0x5];
9355 u8 prio[0x3];
9356 u8 reserved_at_18[0x6];
9357 u8 mode[0x2];
9359 u8 reserved_at_20[0x20];
9361 u8 reserved_at_40[0x10];
9362 u8 min_threshold[0x10];
9364 u8 reserved_at_60[0x10];
9365 u8 max_threshold[0x10];
9367 u8 reserved_at_80[0x10];
9368 u8 mark_probability_denominator[0x10];
9370 u8 reserved_at_a0[0x60];
9374 u8 reserved_at_0[0x8];
9375 u8 local_port[0x8];
9376 u8 reserved_at_10[0x10];
9378 u8 reserved_at_20[0x60];
9380 u8 reserved_at_80[0x1c];
9381 u8 wrps_admin[0x4];
9383 u8 reserved_at_a0[0x1c];
9384 u8 wrps_status[0x4];
9386 u8 reserved_at_c0[0x8];
9387 u8 up_threshold[0x8];
9388 u8 reserved_at_d0[0x8];
9389 u8 down_threshold[0x8];
9391 u8 reserved_at_e0[0x20];
9393 u8 reserved_at_100[0x1c];
9394 u8 srps_admin[0x4];
9396 u8 reserved_at_120[0x1c];
9397 u8 srps_status[0x4];
9399 u8 reserved_at_140[0x40];
9403 u8 reserved_at_0[0x8];
9404 u8 local_port[0x8];
9405 u8 reserved_at_10[0x10];
9407 u8 reserved_at_20[0x8];
9408 u8 lb_cap[0x8];
9409 u8 reserved_at_30[0x8];
9410 u8 lb_en[0x8];
9414 u8 reserved_at_0[0x8];
9415 u8 local_port[0x8];
9416 u8 reserved_at_10[0x10];
9418 u8 reserved_at_20[0x20];
9420 u8 port_profile_mode[0x8];
9421 u8 static_port_profile[0x8];
9422 u8 active_port_profile[0x8];
9423 u8 reserved_at_58[0x8];
9425 u8 retransmission_active[0x8];
9426 u8 fec_mode_active[0x18];
9428 u8 rs_fec_correction_bypass_cap[0x4];
9429 u8 reserved_at_84[0x8];
9430 u8 fec_override_cap_56g[0x4];
9431 u8 fec_override_cap_100g[0x4];
9432 u8 fec_override_cap_50g[0x4];
9433 u8 fec_override_cap_25g[0x4];
9434 u8 fec_override_cap_10g_40g[0x4];
9436 u8 rs_fec_correction_bypass_admin[0x4];
9437 u8 reserved_at_a4[0x8];
9438 u8 fec_override_admin_56g[0x4];
9439 u8 fec_override_admin_100g[0x4];
9440 u8 fec_override_admin_50g[0x4];
9441 u8 fec_override_admin_25g[0x4];
9442 u8 fec_override_admin_10g_40g[0x4];
9444 u8 fec_override_cap_400g_8x[0x10];
9445 u8 fec_override_cap_200g_4x[0x10];
9447 u8 fec_override_cap_100g_2x[0x10];
9448 u8 fec_override_cap_50g_1x[0x10];
9450 u8 fec_override_admin_400g_8x[0x10];
9451 u8 fec_override_admin_200g_4x[0x10];
9453 u8 fec_override_admin_100g_2x[0x10];
9454 u8 fec_override_admin_50g_1x[0x10];
9456 u8 reserved_at_140[0x140];
9460 u8 swid[0x8];
9461 u8 local_port[0x8];
9462 u8 pnat[0x2];
9463 u8 reserved_at_12[0x8];
9464 u8 grp[0x6];
9466 u8 clr[0x1];
9467 u8 reserved_at_21[0x1c];
9468 u8 prio_tc[0x3];
9474 u8 reserved_at_0[0x2];
9475 u8 depth[0x6];
9476 u8 pcie_index[0x8];
9477 u8 node[0x8];
9478 u8 reserved_at_18[0x8];
9480 u8 capability_mask[0x20];
9482 u8 reserved_at_40[0x8];
9483 u8 link_width_enabled[0x8];
9484 u8 link_speed_enabled[0x10];
9486 u8 lane0_physical_position[0x8];
9487 u8 link_width_active[0x8];
9488 u8 link_speed_active[0x10];
9490 u8 num_of_pfs[0x10];
9491 u8 num_of_vfs[0x10];
9493 u8 bdf0[0x10];
9494 u8 reserved_at_b0[0x10];
9496 u8 max_read_request_size[0x4];
9497 u8 max_payload_size[0x4];
9498 u8 reserved_at_c8[0x5];
9499 u8 pwr_status[0x3];
9500 u8 port_type[0x4];
9501 u8 reserved_at_d4[0xb];
9502 u8 lane_reversal[0x1];
9504 u8 reserved_at_e0[0x14];
9505 u8 pci_power[0xc];
9507 u8 reserved_at_100[0x20];
9509 u8 device_status[0x10];
9510 u8 port_state[0x8];
9511 u8 reserved_at_138[0x8];
9513 u8 reserved_at_140[0x10];
9514 u8 receiver_detect_result[0x10];
9516 u8 reserved_at_160[0x20];
9520 u8 reserved_at_0[0x8];
9521 u8 pcie_index[0x8];
9522 u8 reserved_at_10[0xa];
9523 u8 grp[0x6];
9525 u8 clr[0x1];
9526 u8 reserved_at_21[0x1f];
9532 u8 reserved_at_0[0x3];
9533 u8 single_mac[0x1];
9534 u8 reserved_at_4[0x4];
9535 u8 local_port[0x8];
9536 u8 mac_47_32[0x10];
9538 u8 mac_31_0[0x20];
9540 u8 reserved_at_40[0x40];
9544 u8 reserved_at_0[0x8];
9545 u8 local_port[0x8];
9546 u8 reserved_at_10[0x10];
9548 u8 max_mtu[0x10];
9549 u8 reserved_at_30[0x10];
9551 u8 admin_mtu[0x10];
9552 u8 reserved_at_50[0x10];
9554 u8 oper_mtu[0x10];
9555 u8 reserved_at_70[0x10];
9559 u8 reserved_at_0[0x8];
9560 u8 module[0x8];
9561 u8 reserved_at_10[0x10];
9563 u8 reserved_at_20[0x18];
9564 u8 attenuation_5g[0x8];
9566 u8 reserved_at_40[0x18];
9567 u8 attenuation_7g[0x8];
9569 u8 reserved_at_60[0x18];
9570 u8 attenuation_12g[0x8];
9574 u8 reserved_at_0[0x8];
9575 u8 module[0x8];
9576 u8 reserved_at_10[0xc];
9577 u8 module_status[0x4];
9579 u8 reserved_at_20[0x60];
9583 u8 module_state_updated[32][0x8];
9587 u8 reserved_at_0[0x4];
9588 u8 mlpn_status[0x4];
9589 u8 local_port[0x8];
9590 u8 reserved_at_10[0x10];
9592 u8 e[0x1];
9593 u8 reserved_at_21[0x1f];
9597 u8 rxtx[0x1];
9598 u8 reserved_at_1[0x7];
9599 u8 local_port[0x8];
9600 u8 reserved_at_10[0x8];
9601 u8 width[0x8];
9603 u8 lane0_module_mapping[0x20];
9605 u8 lane1_module_mapping[0x20];
9607 u8 lane2_module_mapping[0x20];
9609 u8 lane3_module_mapping[0x20];
9611 u8 reserved_at_a0[0x160];
9615 u8 reserved_at_0[0x8];
9616 u8 module[0x8];
9617 u8 reserved_at_10[0x4];
9618 u8 admin_status[0x4];
9619 u8 reserved_at_18[0x4];
9620 u8 oper_status[0x4];
9622 u8 ase[0x1];
9623 u8 ee[0x1];
9624 u8 reserved_at_22[0x1c];
9625 u8 e[0x2];
9627 u8 reserved_at_40[0x40];
9631 u8 reserved_at_0[0x4];
9632 u8 profile_id[0xc];
9633 u8 reserved_at_10[0x4];
9634 u8 proto_mask[0x4];
9635 u8 reserved_at_18[0x8];
9637 u8 reserved_at_20[0x10];
9638 u8 lane_speed[0x10];
9640 u8 reserved_at_40[0x17];
9641 u8 lpbf[0x1];
9642 u8 fec_mode_policy[0x8];
9644 u8 retransmission_capability[0x8];
9645 u8 fec_mode_capability[0x18];
9647 u8 retransmission_support_admin[0x8];
9648 u8 fec_mode_support_admin[0x18];
9650 u8 retransmission_request_admin[0x8];
9651 u8 fec_mode_request_admin[0x18];
9653 u8 reserved_at_c0[0x80];
9657 u8 reserved_at_0[0x8];
9658 u8 local_port[0x8];
9659 u8 reserved_at_10[0x8];
9660 u8 ib_port[0x8];
9662 u8 reserved_at_20[0x60];
9666 u8 reserved_at_0[0x8];
9667 u8 local_port[0x8];
9668 u8 reserved_at_10[0xd];
9669 u8 lbf_mode[0x3];
9671 u8 reserved_at_20[0x20];
9675 u8 reserved_at_0[0x8];
9676 u8 local_port[0x8];
9677 u8 reserved_at_10[0x10];
9679 u8 dic[0x1];
9680 u8 reserved_at_21[0x19];
9681 u8 ipg[0x4];
9682 u8 reserved_at_3e[0x2];
9686 u8 reserved_at_0[0x8];
9687 u8 local_port[0x8];
9688 u8 reserved_at_10[0x10];
9690 u8 reserved_at_20[0xe0];
9692 u8 port_filter[8][0x20];
9694 u8 port_filter_update_en[8][0x20];
9698 u8 reserved_at_0[0x8];
9699 u8 local_port[0x8];
9700 u8 reserved_at_10[0xb];
9701 u8 ppan_mask_n[0x1];
9702 u8 minor_stall_mask[0x1];
9703 u8 critical_stall_mask[0x1];
9704 u8 reserved_at_1e[0x2];
9706 u8 ppan[0x4];
9707 u8 reserved_at_24[0x4];
9708 u8 prio_mask_tx[0x8];
9709 u8 reserved_at_30[0x8];
9710 u8 prio_mask_rx[0x8];
9712 u8 pptx[0x1];
9713 u8 aptx[0x1];
9714 u8 pptx_mask_n[0x1];
9715 u8 reserved_at_43[0x5];
9716 u8 pfctx[0x8];
9717 u8 reserved_at_50[0x10];
9719 u8 pprx[0x1];
9720 u8 aprx[0x1];
9721 u8 pprx_mask_n[0x1];
9722 u8 reserved_at_63[0x5];
9723 u8 pfcrx[0x8];
9724 u8 reserved_at_70[0x10];
9726 u8 device_stall_minor_watermark[0x10];
9727 u8 device_stall_critical_watermark[0x10];
9729 u8 reserved_at_a0[0x60];
9733 u8 op[0x4];
9734 u8 reserved_at_4[0x4];
9735 u8 local_port[0x8];
9736 u8 reserved_at_10[0x10];
9738 u8 op_admin[0x8];
9739 u8 op_capability[0x8];
9740 u8 op_request[0x8];
9741 u8 op_active[0x8];
9743 u8 admin[0x40];
9745 u8 capability[0x40];
9747 u8 request[0x40];
9749 u8 active[0x40];
9751 u8 reserved_at_140[0x80];
9755 u8 reserved_at_0[0x8];
9756 u8 local_port[0x8];
9757 u8 reserved_at_10[0x10];
9759 u8 reserved_at_20[0xc];
9760 u8 error_count[0x4];
9761 u8 reserved_at_30[0x10];
9763 u8 reserved_at_40[0xc];
9764 u8 lane[0x4];
9765 u8 reserved_at_50[0x8];
9766 u8 error_type[0x8];
9770 u8 reserved_at_0[0x30];
9771 u8 field_select[0x10];
9773 u8 tx_overflow_sense[0x1];
9774 u8 mark_cqe[0x1];
9775 u8 mark_cnp[0x1];
9776 u8 reserved_at_43[0x1b];
9777 u8 tx_lossy_overflow_oper[0x2];
9779 u8 reserved_at_60[0x100];
9783 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1,
9784 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2,
9785 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3,
9789 u8 reserved_at_0[0x1c];
9790 u8 operation[0x4];
9792 u8 freq_adjustment[0x20];
9794 u8 reserved_at_40[0x40];
9796 u8 utc_sec[0x20];
9798 u8 reserved_at_a0[0x2];
9799 u8 utc_nsec[0x1e];
9801 u8 time_adjustment[0x20];
9805 u8 reserved_at_0[0x68];
9806 u8 fec_50G_per_lane_in_pplm[0x1];
9807 u8 reserved_at_69[0x4];
9808 u8 rx_icrc_encapsulated_counter[0x1];
9809 u8 reserved_at_6e[0x4];
9810 u8 ptys_extended_ethernet[0x1];
9811 u8 reserved_at_73[0x3];
9812 u8 pfcc_mask[0x1];
9813 u8 reserved_at_77[0x3];
9814 u8 per_lane_error_counters[0x1];
9815 u8 rx_buffer_fullness_counters[0x1];
9816 u8 ptys_connector_type[0x1];
9817 u8 reserved_at_7d[0x1];
9818 u8 ppcnt_discard_group[0x1];
9819 u8 ppcnt_statistical_group[0x1];
9823 u8 port_access_reg_cap_mask_127_to_96[0x20];
9824 u8 port_access_reg_cap_mask_95_to_64[0x20];
9826 u8 port_access_reg_cap_mask_63_to_36[0x1c];
9827 u8 pplm[0x1];
9828 u8 port_access_reg_cap_mask_34_to_32[0x3];
9830 u8 port_access_reg_cap_mask_31_to_13[0x13];
9831 u8 pbmc[0x1];
9832 u8 pptb[0x1];
9833 u8 port_access_reg_cap_mask_10_to_09[0x2];
9834 u8 ppcnt[0x1];
9835 u8 port_access_reg_cap_mask_07_to_00[0x8];
9839 u8 reserved_at_0[0x8];
9840 u8 feature_group[0x8];
9841 u8 reserved_at_10[0x8];
9842 u8 access_reg_group[0x8];
9844 u8 reserved_at_20[0x20];
9848 u8 reserved_at_0[0x80];
9851 u8 reserved_at_c0[0x80];
9855 u8 reserved_at_0[0x80];
9858 u8 reserved_at_1c0[0xc0];
9862 u8 reserved_at_0[0x5d];
9863 u8 mcia_32dwords[0x1];
9864 u8 out_pulse_duration_ns[0x1];
9865 u8 npps_period[0x1];
9866 u8 reserved_at_60[0xa];
9867 u8 reset_state[0x1];
9868 u8 ptpcyc2realtime_modify[0x1];
9869 u8 reserved_at_6c[0x2];
9870 u8 pci_status_and_power[0x1];
9871 u8 reserved_at_6f[0x5];
9872 u8 mark_tx_action_cnp[0x1];
9873 u8 mark_tx_action_cqe[0x1];
9874 u8 dynamic_tx_overflow[0x1];
9875 u8 reserved_at_77[0x4];
9876 u8 pcie_outbound_stalled[0x1];
9877 u8 tx_overflow_buffer_pkt[0x1];
9878 u8 mtpps_enh_out_per_adj[0x1];
9879 u8 mtpps_fs[0x1];
9880 u8 pcie_performance_group[0x1];
9884 u8 reserved_at_0[0x1c];
9885 u8 mcda[0x1];
9886 u8 mcc[0x1];
9887 u8 mcqi[0x1];
9888 u8 mcqs[0x1];
9890 u8 regs_95_to_87[0x9];
9891 u8 mpegc[0x1];
9892 u8 mtutc[0x1];
9893 u8 regs_84_to_68[0x11];
9894 u8 tracer_registers[0x4];
9896 u8 regs_63_to_46[0x12];
9897 u8 mrtc[0x1];
9898 u8 regs_44_to_32[0xd];
9900 u8 regs_31_to_0[0x20];
9904 u8 regs_127_to_96[0x20];
9906 u8 regs_95_to_64[0x20];
9908 u8 regs_63_to_32[0x20];
9910 u8 regs_31_to_0[0x20];
9914 u8 regs_127_to_99[0x1d];
9915 u8 mirc[0x1];
9916 u8 regs_97_to_96[0x2];
9918 u8 regs_95_to_64[0x20];
9920 u8 regs_63_to_32[0x20];
9922 u8 regs_31_to_0[0x20];
9926 u8 reserved_at_0[0x8];
9927 u8 feature_group[0x8];
9928 u8 reserved_at_10[0x8];
9929 u8 access_reg_group[0x8];
9931 u8 reserved_at_20[0x20];
9937 u8 reserved_at_0[0x80];
9940 u8 reserved_at_c0[0x80];
9944 u8 reserved_at_0[0x80];
9947 u8 reserved_at_1c0[0x80];
9951 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9952 u8 qpdpm[0x1];
9953 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9954 u8 qdpm[0x1];
9955 u8 qpts[0x1];
9956 u8 qcap[0x1];
9957 u8 qcam_access_reg_cap_mask_0[0x1];
9961 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9962 u8 qpts_trust_both[0x1];
9966 u8 reserved_at_0[0x8];
9967 u8 feature_group[0x8];
9968 u8 reserved_at_10[0x8];
9969 u8 access_reg_group[0x8];
9970 u8 reserved_at_20[0x20];
9974 u8 reserved_at_0[0x80];
9977 u8 reserved_at_c0[0x80];
9981 u8 reserved_at_0[0x80];
9984 u8 reserved_at_1c0[0x80];
9988 u8 reserved_at_0[0x18];
9989 u8 core_dump_type[0x8];
9991 u8 reserved_at_20[0x30];
9992 u8 vhca_id[0x10];
9994 u8 reserved_at_60[0x8];
9995 u8 qpn[0x18];
9996 u8 reserved_at_80[0x180];
10000 u8 reserved_at_0[0x8];
10001 u8 local_port[0x8];
10002 u8 reserved_at_10[0x10];
10004 u8 port_capability_mask[4][0x20];
10008 u8 swid[0x8];
10009 u8 local_port[0x8];
10010 u8 reserved_at_10[0x4];
10011 u8 admin_status[0x4];
10012 u8 reserved_at_18[0x4];
10013 u8 oper_status[0x4];
10015 u8 ase[0x1];
10016 u8 ee[0x1];
10017 u8 reserved_at_22[0x1c];
10018 u8 e[0x2];
10020 u8 reserved_at_40[0x40];
10024 u8 reserved_at_0[0x8];
10025 u8 opamp_group[0x8];
10026 u8 reserved_at_10[0xc];
10027 u8 opamp_group_type[0x4];
10029 u8 start_index[0x10];
10030 u8 reserved_at_30[0x4];
10031 u8 num_of_indices[0xc];
10033 u8 index_data[18][0x10];
10037 u8 reserved_at_0[0x8];
10038 u8 local_port[0x8];
10039 u8 reserved_at_10[0x10];
10041 u8 entropy_force_cap[0x1];
10042 u8 entropy_calc_cap[0x1];
10043 u8 entropy_gre_calc_cap[0x1];
10044 u8 reserved_at_23[0xf];
10045 u8 rx_ts_over_crc_cap[0x1];
10046 u8 reserved_at_33[0xb];
10047 u8 fcs_cap[0x1];
10048 u8 reserved_at_3f[0x1];
10050 u8 entropy_force[0x1];
10051 u8 entropy_calc[0x1];
10052 u8 entropy_gre_calc[0x1];
10053 u8 reserved_at_43[0xf];
10054 u8 rx_ts_over_crc[0x1];
10055 u8 reserved_at_53[0xb];
10056 u8 fcs_chk[0x1];
10057 u8 reserved_at_5f[0x1];
10061 u8 reserved_at_0[0x4];
10062 u8 rx_lane[0x4];
10063 u8 reserved_at_8[0x4];
10064 u8 tx_lane[0x4];
10065 u8 reserved_at_10[0x8];
10066 u8 module[0x8];
10070 u8 reserved_at_0[0x6];
10071 u8 lossy[0x1];
10072 u8 epsb[0x1];
10073 u8 reserved_at_8[0x8];
10074 u8 size[0x10];
10076 u8 xoff_threshold[0x10];
10077 u8 xon_threshold[0x10];
10081 u8 node_description[64][0x8];
10085 u8 reserved_at_0[0x18];
10086 u8 power_settings_level[0x8];
10088 u8 reserved_at_20[0x60];
10092 u8 he[0x1];
10093 u8 reserved_at_1[0x1f];
10095 u8 reserved_at_20[0x60];
10099 u8 reserved_at_0[0x20];
10101 u8 mkey[0x20];
10103 u8 addressh_63_32[0x20];
10105 u8 addressl_31_0[0x20];
10109 u8 dc_key[0x40];
10111 u8 ext[0x1];
10112 u8 reserved_at_41[0x7];
10113 u8 destination_qp_dct[0x18];
10115 u8 static_rate[0x4];
10116 u8 sl_eth_prio[0x4];
10117 u8 fl[0x1];
10118 u8 mlid[0x7];
10119 u8 rlid_udp_sport[0x10];
10121 u8 reserved_at_80[0x20];
10123 u8 rmac_47_16[0x20];
10125 u8 rmac_15_0[0x10];
10126 u8 tclass[0x8];
10127 u8 hop_limit[0x8];
10129 u8 reserved_at_e0[0x1];
10130 u8 grh[0x1];
10131 u8 reserved_at_e2[0x2];
10132 u8 src_addr_index[0x8];
10133 u8 flow_label[0x14];
10135 u8 rgid_rip[16][0x8];
10139 u8 reserved_at_0[0x10];
10140 u8 function_id[0x10];
10142 u8 num_pages[0x20];
10144 u8 reserved_at_40[0xa0];
10148 u8 reserved_at_0[0x8];
10149 u8 event_type[0x8];
10150 u8 reserved_at_10[0x8];
10151 u8 event_sub_type[0x8];
10153 u8 reserved_at_20[0xe0];
10157 u8 reserved_at_1e0[0x10];
10158 u8 signature[0x8];
10159 u8 reserved_at_1f8[0x7];
10160 u8 owner[0x1];
10164 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
10168 u8 type[0x8];
10169 u8 reserved_at_8[0x18];
10171 u8 input_length[0x20];
10173 u8 input_mailbox_pointer_63_32[0x20];
10175 u8 input_mailbox_pointer_31_9[0x17];
10176 u8 reserved_at_77[0x9];
10178 u8 command_input_inline_data[16][0x8];
10180 u8 command_output_inline_data[16][0x8];
10182 u8 output_mailbox_pointer_63_32[0x20];
10184 u8 output_mailbox_pointer_31_9[0x17];
10185 u8 reserved_at_1b7[0x9];
10187 u8 output_length[0x20];
10189 u8 token[0x8];
10190 u8 signature[0x8];
10191 u8 reserved_at_1f0[0x8];
10192 u8 status[0x7];
10193 u8 ownership[0x1];
10197 u8 status[0x8];
10198 u8 reserved_at_8[0x18];
10200 u8 syndrome[0x20];
10202 u8 command_output[0x20];
10206 u8 opcode[0x10];
10207 u8 reserved_at_10[0x10];
10209 u8 reserved_at_20[0x10];
10210 u8 op_mod[0x10];
10212 u8 command[][0x20];
10216 u8 mailbox_data[512][0x8];
10218 u8 reserved_at_1000[0x180];
10220 u8 next_pointer_63_32[0x20];
10222 u8 next_pointer_31_10[0x16];
10223 u8 reserved_at_11b6[0xa];
10225 u8 block_number[0x20];
10227 u8 reserved_at_11e0[0x8];
10228 u8 token[0x8];
10229 u8 ctrl_signature[0x8];
10230 u8 signature[0x8];
10234 u8 ptag_63_32[0x20];
10236 u8 ptag_31_8[0x18];
10237 u8 reserved_at_38[0x6];
10238 u8 wr_en[0x1];
10239 u8 rd_en[0x1];
10243 u8 status[0x8];
10244 u8 reserved_at_8[0x18];
10246 u8 syndrome[0x20];
10248 u8 reserved_at_40[0x10];
10249 u8 rol_mode[0x8];
10250 u8 wol_mode[0x8];
10252 u8 reserved_at_60[0x20];
10256 u8 opcode[0x10];
10257 u8 reserved_at_10[0x10];
10259 u8 reserved_at_20[0x10];
10260 u8 op_mod[0x10];
10262 u8 reserved_at_40[0x40];
10266 u8 status[0x8];
10267 u8 reserved_at_8[0x18];
10269 u8 syndrome[0x20];
10271 u8 reserved_at_40[0x40];
10275 u8 opcode[0x10];
10276 u8 reserved_at_10[0x10];
10278 u8 reserved_at_20[0x10];
10279 u8 op_mod[0x10];
10281 u8 rol_mode_valid[0x1];
10282 u8 wol_mode_valid[0x1];
10283 u8 reserved_at_42[0xe];
10284 u8 rol_mode[0x8];
10285 u8 wol_mode[0x8];
10287 u8 reserved_at_60[0x20];
10291 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
10292 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
10293 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
10297 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
10298 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
10299 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
10303 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
10304 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
10305 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
10306 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
10307 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
10308 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
10309 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
10310 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
10311 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
10312 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
10313 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
10317 u8 fw_rev_minor[0x10];
10318 u8 fw_rev_major[0x10];
10320 u8 cmd_interface_rev[0x10];
10321 u8 fw_rev_subminor[0x10];
10323 u8 reserved_at_40[0x40];
10325 u8 cmdq_phy_addr_63_32[0x20];
10327 u8 cmdq_phy_addr_31_12[0x14];
10328 u8 reserved_at_b4[0x2];
10329 u8 nic_interface[0x2];
10330 u8 log_cmdq_size[0x4];
10331 u8 log_cmdq_stride[0x4];
10333 u8 command_doorbell_vector[0x20];
10335 u8 reserved_at_e0[0xf00];
10337 u8 initializing[0x1];
10338 u8 reserved_at_fe1[0x4];
10339 u8 nic_interface_supported[0x3];
10340 u8 embedded_cpu[0x1];
10341 u8 reserved_at_fe9[0x17];
10345 u8 no_dram_nic_offset[0x20];
10347 u8 reserved_at_1220[0x6e40];
10349 u8 reserved_at_8060[0x1f];
10350 u8 clear_int[0x1];
10352 u8 health_syndrome[0x8];
10353 u8 health_counter[0x18];
10355 u8 reserved_at_80a0[0x17fc0];
10359 u8 reserved_at_0[0xc];
10360 u8 cap_number_of_pps_pins[0x4];
10361 u8 reserved_at_10[0x4];
10362 u8 cap_max_num_of_pps_in_pins[0x4];
10363 u8 reserved_at_18[0x4];
10364 u8 cap_max_num_of_pps_out_pins[0x4];
10366 u8 reserved_at_20[0x13];
10367 u8 cap_log_min_npps_period[0x5];
10368 u8 reserved_at_38[0x3];
10369 u8 cap_log_min_out_pulse_duration_ns[0x5];
10371 u8 reserved_at_40[0x4];
10372 u8 cap_pin_3_mode[0x4];
10373 u8 reserved_at_48[0x4];
10374 u8 cap_pin_2_mode[0x4];
10375 u8 reserved_at_50[0x4];
10376 u8 cap_pin_1_mode[0x4];
10377 u8 reserved_at_58[0x4];
10378 u8 cap_pin_0_mode[0x4];
10380 u8 reserved_at_60[0x4];
10381 u8 cap_pin_7_mode[0x4];
10382 u8 reserved_at_68[0x4];
10383 u8 cap_pin_6_mode[0x4];
10384 u8 reserved_at_70[0x4];
10385 u8 cap_pin_5_mode[0x4];
10386 u8 reserved_at_78[0x4];
10387 u8 cap_pin_4_mode[0x4];
10389 u8 field_select[0x20];
10390 u8 reserved_at_a0[0x20];
10392 u8 npps_period[0x40];
10394 u8 enable[0x1];
10395 u8 reserved_at_101[0xb];
10396 u8 pattern[0x4];
10397 u8 reserved_at_110[0x4];
10398 u8 pin_mode[0x4];
10399 u8 pin[0x8];
10401 u8 reserved_at_120[0x2];
10402 u8 out_pulse_duration_ns[0x1e];
10404 u8 time_stamp[0x40];
10406 u8 out_pulse_duration[0x10];
10407 u8 out_periodic_adjustment[0x10];
10408 u8 enhanced_out_periodic_adjustment[0x20];
10410 u8 reserved_at_1c0[0x20];
10414 u8 reserved_at_0[0x18];
10415 u8 pin[0x8];
10416 u8 event_arm[0x1];
10417 u8 reserved_at_21[0x1b];
10418 u8 event_generation_mode[0x4];
10419 u8 reserved_at_40[0x40];
10423 u8 last_index_flag[0x1];
10424 u8 reserved_at_1[0x7];
10425 u8 fw_device[0x8];
10426 u8 component_index[0x10];
10428 u8 reserved_at_20[0x10];
10429 u8 identifier[0x10];
10431 u8 reserved_at_40[0x17];
10432 u8 component_status[0x5];
10433 u8 component_update_state[0x4];
10435 u8 last_update_state_changer_type[0x4];
10436 u8 last_update_state_changer_host_id[0x4];
10437 u8 reserved_at_68[0x18];
10441 u8 supported_info_bitmask[0x20];
10443 u8 component_size[0x20];
10445 u8 max_component_size[0x20];
10447 u8 log_mcda_word_size[0x4];
10448 u8 reserved_at_64[0xc];
10449 u8 mcda_max_write_size[0x10];
10451 u8 rd_en[0x1];
10452 u8 reserved_at_81[0x1];
10453 u8 match_chip_id[0x1];
10454 u8 match_psid[0x1];
10455 u8 check_user_timestamp[0x1];
10456 u8 match_base_guid_mac[0x1];
10457 u8 reserved_at_86[0x1a];
10461 u8 reserved_at_0[0x2];
10462 u8 build_time_valid[0x1];
10463 u8 user_defined_time_valid[0x1];
10464 u8 reserved_at_4[0x14];
10465 u8 version_string_length[0x8];
10467 u8 version[0x20];
10469 u8 build_time[0x40];
10471 u8 user_defined_time[0x40];
10473 u8 build_tool_version[0x20];
10475 u8 reserved_at_e0[0x20];
10477 u8 version_string[92][0x8];
10481 u8 pending_server_ac_power_cycle[0x1];
10482 u8 pending_server_dc_power_cycle[0x1];
10483 u8 pending_server_reboot[0x1];
10484 u8 pending_fw_reset[0x1];
10485 u8 auto_activate[0x1];
10486 u8 all_hosts_sync[0x1];
10487 u8 device_hw_reset[0x1];
10488 u8 reserved_at_7[0x19];
10498 u8 read_pending_component[0x1];
10499 u8 reserved_at_1[0xf];
10500 u8 component_index[0x10];
10502 u8 reserved_at_20[0x20];
10504 u8 reserved_at_40[0x1b];
10505 u8 info_type[0x5];
10507 u8 info_size[0x20];
10509 u8 offset[0x20];
10511 u8 reserved_at_a0[0x10];
10512 u8 data_size[0x10];
10518 u8 reserved_at_0[0x4];
10519 u8 time_elapsed_since_last_cmd[0xc];
10520 u8 reserved_at_10[0x8];
10521 u8 instruction[0x8];
10523 u8 reserved_at_20[0x10];
10524 u8 component_index[0x10];
10526 u8 reserved_at_40[0x8];
10527 u8 update_handle[0x18];
10529 u8 handle_owner_type[0x4];
10530 u8 handle_owner_host_id[0x4];
10531 u8 reserved_at_68[0x1];
10532 u8 control_progress[0x7];
10533 u8 error_code[0x8];
10534 u8 reserved_at_78[0x4];
10535 u8 control_state[0x4];
10537 u8 component_size[0x20];
10539 u8 reserved_at_a0[0x60];
10543 u8 reserved_at_0[0x8];
10544 u8 update_handle[0x18];
10546 u8 offset[0x20];
10548 u8 reserved_at_40[0x10];
10549 u8 size[0x10];
10551 u8 reserved_at_60[0x20];
10553 u8 data[][0x20];
10557 MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10565 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10570 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10576 u8 reserved_at_0[0x20];
10578 u8 reserved_at_20[0x2];
10579 u8 pci_sync_for_fw_update_start[0x1];
10580 u8 pci_sync_for_fw_update_resp[0x2];
10581 u8 rst_type_sel[0x3];
10582 u8 reserved_at_28[0x4];
10583 u8 reset_state[0x4];
10584 u8 reset_type[0x8];
10585 u8 reset_level[0x8];
10589 u8 reserved_at_0[0x18];
10590 u8 status_code[0x8];
10592 u8 reserved_at_20[0x20];
10596 u8 reserved_at_0[0x10];
10597 u8 monitor_opcode[0x10];
10602 u8 reserved_at_0[0x20];
10607 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10611 u8 reserved_at_0[0x10];
10612 u8 group_opcode[0x10];
10616 u8 reserved_at_40[0x20];
10618 u8 status_message[59][0x20];
10623 u8 reserved_at_0[0x7c0];
10627 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1,
10631 u8 reserved_at_0[0x8];
10632 u8 local_port[0x8];
10633 u8 pnat[0x2];
10634 u8 reserved_at_12[0xe];
10636 u8 reserved_at_20[0x18];
10637 u8 page_select[0x8];
10643 u8 time_synced[0x1];
10644 u8 reserved_at_1[0x1f];
10646 u8 reserved_at_20[0x20];
10648 u8 time_h[0x20];
10650 u8 time_l[0x20];
10715 u8 reserved_at_0[0x60e0];
10720 u8 reserved_at_0[0x200];
10725 u8 reserved_at_0[0x20060];
10729 u8 status[0x8];
10730 u8 reserved_at_8[0x18];
10732 u8 syndrome[0x20];
10734 u8 reserved_at_40[0x40];
10738 u8 opcode[0x10];
10739 u8 reserved_at_10[0x10];
10741 u8 reserved_at_20[0x10];
10742 u8 op_mod[0x10];
10744 u8 other_vport[0x1];
10745 u8 reserved_at_41[0xf];
10746 u8 vport_number[0x10];
10748 u8 reserved_at_60[0x20];
10750 u8 table_type[0x8];
10751 u8 reserved_at_88[0x7];
10752 u8 table_of_other_vport[0x1];
10753 u8 table_vport_number[0x10];
10755 u8 reserved_at_a0[0x8];
10756 u8 table_id[0x18];
10758 u8 reserved_at_c0[0x8];
10759 u8 underlay_qpn[0x18];
10760 u8 table_eswitch_owner_vhca_id_valid[0x1];
10761 u8 reserved_at_e1[0xf];
10762 u8 table_eswitch_owner_vhca_id[0x10];
10763 u8 reserved_at_100[0x100];
10767 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
10772 u8 status[0x8];
10773 u8 reserved_at_8[0x18];
10775 u8 syndrome[0x20];
10777 u8 reserved_at_40[0x40];
10781 u8 opcode[0x10];
10782 u8 reserved_at_10[0x10];
10784 u8 reserved_at_20[0x10];
10785 u8 op_mod[0x10];
10787 u8 other_vport[0x1];
10788 u8 reserved_at_41[0xf];
10789 u8 vport_number[0x10];
10791 u8 reserved_at_60[0x10];
10792 u8 modify_field_select[0x10];
10794 u8 table_type[0x8];
10795 u8 reserved_at_88[0x18];
10797 u8 reserved_at_a0[0x8];
10798 u8 table_id[0x18];
10804 u8 g[0x1];
10805 u8 b[0x1];
10806 u8 r[0x1];
10807 u8 reserved_at_3[0x9];
10808 u8 group[0x4];
10809 u8 reserved_at_10[0x9];
10810 u8 bw_allocation[0x7];
10812 u8 reserved_at_20[0xc];
10813 u8 max_bw_units[0x4];
10814 u8 reserved_at_30[0x8];
10815 u8 max_bw_value[0x8];
10819 u8 reserved_at_0[0x2];
10820 u8 r[0x1];
10821 u8 reserved_at_3[0x1d];
10823 u8 reserved_at_20[0xc];
10824 u8 max_bw_units[0x4];
10825 u8 reserved_at_30[0x8];
10826 u8 max_bw_value[0x8];
10830 u8 reserved_at_0[0x8];
10831 u8 port_number[0x8];
10832 u8 reserved_at_10[0x30];
10834 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
10839 u8 e[0x1];
10840 u8 reserved_at_01[0x0b];
10841 u8 prio[0x04];
10845 u8 reserved_at_0[0x8];
10846 u8 local_port[0x8];
10847 u8 reserved_at_10[0x10];
10852 u8 reserved_at_0[0x8];
10853 u8 local_port[0x8];
10854 u8 reserved_at_10[0x2d];
10855 u8 trust_state[0x3];
10859 u8 reserved_at_0[0x2];
10860 u8 mm[0x2];
10861 u8 reserved_at_4[0x4];
10862 u8 local_port[0x8];
10863 u8 reserved_at_10[0x6];
10864 u8 cm[0x1];
10865 u8 um[0x1];
10866 u8 pm[0x8];
10868 u8 prio_x_buff[0x20];
10870 u8 pm_msb[0x8];
10871 u8 reserved_at_48[0x10];
10872 u8 ctrl_buff[0x4];
10873 u8 untagged_buff[0x4];
10877 u8 reserved_at_0[0x8];
10878 u8 feature_group[0x8];
10879 u8 reserved_at_10[0x8];
10880 u8 access_reg_group[0x8];
10882 u8 reserved_at_20[0x20];
10884 u8 sb_access_reg_cap_mask[4][0x20];
10886 u8 reserved_at_c0[0x80];
10888 u8 sb_feature_cap_mask[4][0x20];
10890 u8 reserved_at_1c0[0x40];
10892 u8 cap_total_buffer_size[0x20];
10894 u8 cap_cell_size[0x10];
10895 u8 cap_max_pg_buffers[0x8];
10896 u8 cap_num_pool_supported[0x8];
10898 u8 reserved_at_240[0x8];
10899 u8 cap_sbsr_stat_size[0x8];
10900 u8 cap_max_tclass_data[0x8];
10901 u8 cap_max_cpu_ingress_tclass_sb[0x8];
10905 u8 reserved_at_0[0x8];
10906 u8 local_port[0x8];
10907 u8 reserved_at_10[0x10];
10909 u8 xoff_timer_value[0x10];
10910 u8 xoff_refresh[0x10];
10912 u8 reserved_at_40[0x9];
10913 u8 fullness_threshold[0x7];
10914 u8 port_buffer_size[0x10];
10918 u8 reserved_at_2e0[0x80];
10922 u8 reserved_at_0[0x8];
10923 u8 port_number[0x8];
10924 u8 reserved_at_10[0xd];
10925 u8 prio[0x3];
10927 u8 reserved_at_20[0x1d];
10928 u8 tclass[0x3];
10932 u8 l[0x1];
10933 u8 reserved_at_1[0x7];
10934 u8 module[0x8];
10935 u8 reserved_at_10[0x8];
10936 u8 status[0x8];
10938 u8 i2c_device_address[0x8];
10939 u8 page_number[0x8];
10940 u8 device_address[0x10];
10942 u8 reserved_at_40[0x10];
10943 u8 size[0x10];
10945 u8 reserved_at_60[0x20];
10947 u8 dword_0[0x20];
10948 u8 dword_1[0x20];
10949 u8 dword_2[0x20];
10950 u8 dword_3[0x20];
10951 u8 dword_4[0x20];
10952 u8 dword_5[0x20];
10953 u8 dword_6[0x20];
10954 u8 dword_7[0x20];
10955 u8 dword_8[0x20];
10956 u8 dword_9[0x20];
10957 u8 dword_10[0x20];
10958 u8 dword_11[0x20];
10962 u8 dcbx_cee_cap[0x1];
10963 u8 dcbx_ieee_cap[0x1];
10964 u8 dcbx_standby_cap[0x1];
10965 u8 reserved_at_3[0x5];
10966 u8 port_number[0x8];
10967 u8 reserved_at_10[0xa];
10969 u8 reserved_at_20[0x15];
10970 u8 version_oper[0x3];
10972 u8 version_admin[0x3];
10973 u8 willing_admin[0x1];
10974 u8 reserved_at_41[0x3];
10975 u8 pfc_cap_oper[0x4];
10976 u8 reserved_at_48[0x4];
10977 u8 pfc_cap_admin[0x4];
10978 u8 reserved_at_50[0x4];
10979 u8 num_of_tc_oper[0x4];
10980 u8 reserved_at_58[0x4];
10981 u8 num_of_tc_admin[0x4];
10982 u8 remote_willing[0x1];
10985 u8 reserved_at_68[0x14];
10986 u8 remote_num_of_tc[0x4];
10987 u8 reserved_at_80[0x18];
10988 u8 error[0x8];
10989 u8 reserved_at_a0[0x160];
10993 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
10999 u8 fdb_selection_mode[0x1];
11000 u8 reserved_at_1[0x14];
11001 u8 port_select_mode[0x3];
11002 u8 reserved_at_18[0x5];
11003 u8 lag_state[0x3];
11005 u8 reserved_at_20[0xc];
11006 u8 active_port[0x4];
11007 u8 reserved_at_30[0x4];
11008 u8 tx_remap_affinity_2[0x4];
11009 u8 reserved_at_38[0x4];
11010 u8 tx_remap_affinity_1[0x4];
11014 u8 status[0x8];
11015 u8 reserved_at_8[0x18];
11017 u8 syndrome[0x20];
11019 u8 reserved_at_40[0x40];
11023 u8 opcode[0x10];
11024 u8 reserved_at_10[0x10];
11026 u8 reserved_at_20[0x10];
11027 u8 op_mod[0x10];
11033 u8 status[0x8];
11034 u8 reserved_at_8[0x18];
11036 u8 syndrome[0x20];
11038 u8 reserved_at_40[0x40];
11042 u8 opcode[0x10];
11043 u8 reserved_at_10[0x10];
11045 u8 reserved_at_20[0x10];
11046 u8 op_mod[0x10];
11048 u8 reserved_at_40[0x20];
11049 u8 field_select[0x20];
11055 u8 status[0x8];
11056 u8 reserved_at_8[0x18];
11058 u8 syndrome[0x20];
11064 u8 opcode[0x10];
11065 u8 reserved_at_10[0x10];
11067 u8 reserved_at_20[0x10];
11068 u8 op_mod[0x10];
11070 u8 reserved_at_40[0x40];
11074 u8 status[0x8];
11075 u8 reserved_at_8[0x18];
11077 u8 syndrome[0x20];
11079 u8 reserved_at_40[0x40];
11083 u8 opcode[0x10];
11084 u8 reserved_at_10[0x10];
11086 u8 reserved_at_20[0x10];
11087 u8 op_mod[0x10];
11089 u8 reserved_at_40[0x40];
11093 u8 status[0x8];
11094 u8 reserved_at_8[0x18];
11096 u8 syndrome[0x20];
11098 u8 reserved_at_40[0x40];
11102 u8 opcode[0x10];
11103 u8 reserved_at_10[0x10];
11105 u8 reserved_at_20[0x10];
11106 u8 op_mod[0x10];
11108 u8 reserved_at_40[0x40];
11112 u8 status[0x8];
11113 u8 reserved_at_8[0x18];
11115 u8 syndrome[0x20];
11117 u8 reserved_at_40[0x40];
11121 u8 opcode[0x10];
11122 u8 reserved_at_10[0x10];
11124 u8 reserved_at_20[0x10];
11125 u8 op_mod[0x10];
11127 u8 reserved_at_40[0x40];
11136 u8 opcode[0x10];
11137 u8 uid[0x10];
11139 u8 reserved_at_20[0x10];
11140 u8 op_mod[0x10];
11142 u8 reserved_at_40[0x20];
11144 u8 reserved_at_60[0x18];
11145 u8 memic_operation_type[0x8];
11147 u8 memic_start_addr[0x40];
11149 u8 reserved_at_c0[0x140];
11153 u8 status[0x8];
11154 u8 reserved_at_8[0x18];
11156 u8 syndrome[0x20];
11158 u8 reserved_at_40[0x40];
11160 u8 memic_operation_addr[0x40];
11162 u8 reserved_at_c0[0x140];
11166 u8 opcode[0x10];
11167 u8 reserved_at_10[0x10];
11169 u8 reserved_at_20[0x10];
11170 u8 op_mod[0x10];
11172 u8 reserved_at_30[0x20];
11174 u8 reserved_at_40[0x18];
11175 u8 log_memic_addr_alignment[0x8];
11177 u8 range_start_addr[0x40];
11179 u8 range_size[0x20];
11181 u8 memic_size[0x20];
11185 u8 status[0x8];
11186 u8 reserved_at_8[0x18];
11188 u8 syndrome[0x20];
11190 u8 memic_start_addr[0x40];
11194 u8 opcode[0x10];
11195 u8 reserved_at_10[0x10];
11197 u8 reserved_at_20[0x10];
11198 u8 op_mod[0x10];
11200 u8 reserved_at_40[0x40];
11202 u8 memic_start_addr[0x40];
11204 u8 memic_size[0x20];
11206 u8 reserved_at_e0[0x20];
11210 u8 status[0x8];
11211 u8 reserved_at_8[0x18];
11213 u8 syndrome[0x20];
11215 u8 reserved_at_40[0x40];
11219 u8 reserved_at_0[0x80];
11221 u8 ats[0x1];
11222 u8 reserved_at_81[0x1a];
11223 u8 log_page_size[0x5];
11225 u8 page_offset[0x20];
11227 u8 num_of_mtt[0x40];
11233 u8 cap[0x20];
11235 u8 reserved_at_20[0x160];
11239 u8 modify_field_select[0x40];
11241 u8 reserved_at_40[0x18];
11242 u8 log_sw_icm_size[0x8];
11244 u8 reserved_at_60[0x20];
11246 u8 sw_icm_start_addr[0x40];
11248 u8 reserved_at_c0[0x140];
11252 u8 modify_field_select[0x40];
11254 u8 reserved_at_40[0x18];
11255 u8 geneve_option_fte_index[0x8];
11257 u8 option_class[0x10];
11258 u8 option_type[0x8];
11259 u8 reserved_at_78[0x3];
11260 u8 option_data_length[0x5];
11262 u8 reserved_at_80[0x180];
11266 u8 opcode[0x10];
11267 u8 uid[0x10];
11269 u8 reserved_at_20[0x10];
11270 u8 op_mod[0x10];
11272 u8 reserved_at_40[0x40];
11278 u8 status[0x8];
11279 u8 reserved_at_8[0x18];
11281 u8 syndrome[0x20];
11283 u8 reserved_at_40[0x8];
11284 u8 umem_id[0x18];
11286 u8 reserved_at_60[0x20];
11290 u8 opcode[0x10];
11291 u8 uid[0x10];
11293 u8 reserved_at_20[0x10];
11294 u8 op_mod[0x10];
11296 u8 reserved_at_40[0x8];
11297 u8 umem_id[0x18];
11299 u8 reserved_at_60[0x20];
11303 u8 status[0x8];
11304 u8 reserved_at_8[0x18];
11306 u8 syndrome[0x20];
11308 u8 reserved_at_40[0x40];
11312 u8 opcode[0x10];
11313 u8 reserved_at_10[0x10];
11315 u8 reserved_at_20[0x10];
11316 u8 op_mod[0x10];
11318 u8 reserved_at_40[0x40];
11324 u8 status[0x8];
11325 u8 reserved_at_8[0x18];
11327 u8 syndrome[0x20];
11329 u8 reserved_at_40[0x10];
11330 u8 uid[0x10];
11332 u8 reserved_at_60[0x20];
11336 u8 opcode[0x10];
11337 u8 reserved_at_10[0x10];
11339 u8 reserved_at_20[0x10];
11340 u8 op_mod[0x10];
11342 u8 reserved_at_40[0x10];
11343 u8 uid[0x10];
11345 u8 reserved_at_60[0x20];
11349 u8 status[0x8];
11350 u8 reserved_at_8[0x18];
11352 u8 syndrome[0x20];
11354 u8 reserved_at_40[0x40];
11368 u8 string_db_base_address[0x20];
11370 u8 reserved_at_20[0x8];
11371 u8 string_db_size[0x18];
11375 u8 trace_owner[0x1];
11376 u8 trace_to_memory[0x1];
11377 u8 reserved_at_2[0x4];
11378 u8 trc_ver[0x2];
11379 u8 reserved_at_8[0x14];
11380 u8 num_string_db[0x4];
11382 u8 first_string_trace[0x8];
11383 u8 num_string_trace[0x8];
11384 u8 reserved_at_30[0x28];
11386 u8 log_max_trace_buffer_size[0x8];
11388 u8 reserved_at_60[0x20];
11392 u8 reserved_at_280[0x180];
11396 u8 reserved_at_0[0x1c];
11397 u8 trace_mode[0x4];
11398 u8 reserved_at_20[0x18];
11399 u8 log_trace_buffer_size[0x8];
11400 u8 trace_mkey[0x20];
11401 u8 reserved_at_60[0x3a0];
11405 u8 string_db_index[0x4];
11406 u8 reserved_at_4[0x4];
11407 u8 read_size[0x18];
11408 u8 start_offset[0x20];
11413 u8 trace_status[0x2];
11414 u8 reserved_at_2[0x2];
11415 u8 arm_event[0x1];
11416 u8 reserved_at_5[0xb];
11417 u8 modify_field_select[0x10];
11418 u8 reserved_at_20[0x2b];
11419 u8 current_timestamp52_32[0x15];
11420 u8 current_timestamp31_0[0x20];
11421 u8 reserved_at_80[0x180];
11425 u8 host_number[0x8];
11426 u8 reserved_at_8[0x7];
11427 u8 host_pf_disabled[0x1];
11428 u8 host_num_of_vfs[0x10];
11430 u8 host_total_vfs[0x10];
11431 u8 host_pci_bus[0x10];
11433 u8 reserved_at_40[0x10];
11434 u8 host_pci_device[0x10];
11436 u8 reserved_at_60[0x10];
11437 u8 host_pci_function[0x10];
11439 u8 reserved_at_80[0x180];
11443 u8 opcode[0x10];
11444 u8 reserved_at_10[0x10];
11446 u8 reserved_at_20[0x10];
11447 u8 op_mod[0x10];
11449 u8 reserved_at_40[0x40];
11453 u8 status[0x8];
11454 u8 reserved_at_8[0x18];
11456 u8 syndrome[0x20];
11458 u8 reserved_at_40[0x40];
11462 u8 reserved_at_280[0x180];
11463 u8 host_sf_enable[][0x40];
11467 u8 reserved_at_0[0x10];
11468 u8 log_num_sf[0x8];
11469 u8 log_sf_bar_size[0x8];
11473 u8 status[0x8];
11474 u8 reserved_at_8[0x18];
11476 u8 syndrome[0x20];
11478 u8 reserved_at_40[0x18];
11479 u8 num_sf_partitions[0x8];
11481 u8 reserved_at_60[0x20];
11487 u8 opcode[0x10];
11488 u8 reserved_at_10[0x10];
11490 u8 reserved_at_20[0x10];
11491 u8 op_mod[0x10];
11493 u8 reserved_at_40[0x40];
11497 u8 status[0x8];
11498 u8 reserved_at_8[0x18];
11500 u8 syndrome[0x20];
11502 u8 reserved_at_40[0x40];
11506 u8 opcode[0x10];
11507 u8 reserved_at_10[0x10];
11509 u8 reserved_at_20[0x10];
11510 u8 op_mod[0x10];
11512 u8 reserved_at_40[0x10];
11513 u8 function_id[0x10];
11515 u8 reserved_at_60[0x20];
11519 u8 status[0x8];
11520 u8 reserved_at_8[0x18];
11522 u8 syndrome[0x20];
11524 u8 reserved_at_40[0x40];
11528 u8 opcode[0x10];
11529 u8 reserved_at_10[0x10];
11531 u8 reserved_at_20[0x10];
11532 u8 op_mod[0x10];
11534 u8 reserved_at_40[0x10];
11535 u8 function_id[0x10];
11537 u8 reserved_at_60[0x20];
11541 u8 reserved_at_0[0x10];
11542 u8 obj_type[0x10];
11544 u8 obj_id[0x20];
11548 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11549 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11550 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11551 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
11555 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11556 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11557 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11558 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
11559 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
11567 u8 modify_field_select[0x40];
11568 u8 full_offload[0x1];
11569 u8 reserved_at_41[0x1];
11570 u8 esn_en[0x1];
11571 u8 esn_overlap[0x1];
11572 u8 reserved_at_44[0x2];
11573 u8 icv_length[0x2];
11574 u8 reserved_at_48[0x4];
11575 u8 aso_return_reg[0x4];
11576 u8 reserved_at_50[0x10];
11578 u8 esn_msb[0x20];
11580 u8 reserved_at_80[0x8];
11581 u8 dekn[0x18];
11583 u8 salt[0x20];
11585 u8 implicit_iv[0x40];
11587 u8 reserved_at_100[0x700];
11596 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11611 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
11615 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0,
11616 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1,
11617 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
11618 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
11621 #define MLX5_MACSEC_ASO_INC_SN 0x2
11622 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
11625 u8 valid[0x1];
11626 u8 reserved_at_1[0x1];
11627 u8 mode[0x2];
11628 u8 window_size[0x2];
11629 u8 soft_lifetime_arm[0x1];
11630 u8 hard_lifetime_arm[0x1];
11631 u8 remove_flow_enable[0x1];
11632 u8 epn_event_arm[0x1];
11633 u8 reserved_at_a[0x16];
11635 u8 remove_flow_packet_count[0x20];
11637 u8 remove_flow_soft_lifetime[0x20];
11639 u8 reserved_at_60[0x80];
11641 u8 mode_parameter[0x20];
11643 u8 replay_protection_window[8][0x20];
11647 u8 modify_field_select[0x40];
11649 u8 confidentiality_en[0x1];
11650 u8 reserved_at_41[0x1];
11651 u8 epn_en[0x1];
11652 u8 epn_overlap[0x1];
11653 u8 reserved_at_44[0x2];
11654 u8 confidentiality_offset[0x2];
11655 u8 reserved_at_48[0x4];
11656 u8 aso_return_reg[0x4];
11657 u8 reserved_at_50[0x10];
11659 u8 epn_msb[0x20];
11661 u8 reserved_at_80[0x8];
11662 u8 dekn[0x18];
11664 u8 reserved_at_a0[0x20];
11666 u8 sci[0x40];
11668 u8 reserved_at_100[0x8];
11669 u8 macsec_aso_access_pd[0x18];
11671 u8 reserved_at_120[0x60];
11673 u8 salt[3][0x20];
11675 u8 reserved_at_1e0[0x20];
11691 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
11701 u8 modify_field_select[0x40];
11703 u8 reserved_at_40[0x14];
11704 u8 key_size[0x4];
11705 u8 reserved_at_58[0x4];
11706 u8 key_type[0x4];
11708 u8 reserved_at_60[0x8];
11709 u8 pd[0x18];
11711 u8 reserved_at_80[0x180];
11712 u8 key[8][0x20];
11714 u8 reserved_at_300[0x500];
11723 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0,
11724 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1,
11725 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2,
11726 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3,
11730 u8 valid[0x1];
11731 u8 bucket_overflow[0x1];
11732 u8 start_color[0x2];
11733 u8 both_buckets_on_green[0x1];
11734 u8 reserved_at_5[0x1];
11735 u8 meter_mode[0x2];
11736 u8 reserved_at_8[0x18];
11738 u8 reserved_at_20[0x20];
11740 u8 reserved_at_40[0x3];
11741 u8 cbs_exponent[0x5];
11742 u8 cbs_mantissa[0x8];
11743 u8 reserved_at_50[0x3];
11744 u8 cir_exponent[0x5];
11745 u8 cir_mantissa[0x8];
11747 u8 reserved_at_60[0x20];
11749 u8 reserved_at_80[0x3];
11750 u8 ebs_exponent[0x5];
11751 u8 ebs_mantissa[0x8];
11752 u8 reserved_at_90[0x3];
11753 u8 eir_exponent[0x5];
11754 u8 eir_mantissa[0x8];
11756 u8 reserved_at_a0[0x60];
11760 u8 modify_field_select[0x40];
11762 u8 reserved_at_40[0x40];
11764 u8 reserved_at_80[0x8];
11765 u8 meter_aso_access_pd[0x18];
11767 u8 reserved_at_a0[0x160];
11778 u8 modify_field_select[0x40];
11780 u8 table_type[0x8];
11781 u8 level[0x8];
11782 u8 reserved_at_50[0xf];
11783 u8 ignore_flow_level[0x1];
11785 u8 sample_ratio[0x20];
11787 u8 reserved_at_80[0x8];
11788 u8 sample_table_id[0x18];
11790 u8 reserved_at_a0[0x8];
11791 u8 default_table_id[0x18];
11793 u8 sw_steering_icm_address_rx[0x40];
11794 u8 sw_steering_icm_address_tx[0x40];
11796 u8 reserved_at_140[0xa0];
11810 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11811 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11815 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11816 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
11817 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_MACSEC = 0x4,
11821 u8 const_2[0x2];
11822 u8 tls_version[0x4];
11823 u8 const_1[0x2];
11824 u8 reserved_at_8[0x14];
11825 u8 encryption_standard[0x4];
11827 u8 reserved_at_20[0x20];
11829 u8 initial_record_number[0x40];
11831 u8 resync_tcp_sn[0x20];
11833 u8 gcm_iv[0x20];
11835 u8 implicit_iv[0x40];
11837 u8 reserved_at_100[0x8];
11838 u8 dek_index[0x18];
11840 u8 reserved_at_120[0xe0];
11844 u8 next_record_tcp_sn[0x20];
11846 u8 hw_resync_tcp_sn[0x20];
11848 u8 record_tracker_state[0x2];
11849 u8 auth_state[0x2];
11850 u8 reserved_at_44[0x4];
11851 u8 hw_offset_record_number[0x18];
11855 MLX5_MTT_PERM_READ = 1 << 0,
11861 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0,
11862 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1,
11866 u8 opcode[0x10];
11867 u8 uid[0x10];
11869 u8 reserved_at_20[0x10];
11870 u8 op_mod[0x10];
11872 u8 reserved_at_40[0x10];
11873 u8 vhca_id[0x10];
11875 u8 reserved_at_60[0x20];
11879 u8 status[0x8];
11880 u8 reserved_at_8[0x18];
11882 u8 syndrome[0x20];
11884 u8 reserved_at_40[0x40];
11888 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0,
11889 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1,
11893 u8 opcode[0x10];
11894 u8 uid[0x10];
11896 u8 reserved_at_20[0x10];
11897 u8 op_mod[0x10];
11899 u8 reserved_at_40[0x10];
11900 u8 vhca_id[0x10];
11902 u8 reserved_at_60[0x20];
11906 u8 status[0x8];
11907 u8 reserved_at_8[0x18];
11909 u8 syndrome[0x20];
11911 u8 reserved_at_40[0x40];
11915 u8 opcode[0x10];
11916 u8 uid[0x10];
11918 u8 reserved_at_20[0x10];
11919 u8 op_mod[0x10];
11921 u8 reserved_at_40[0x10];
11922 u8 vhca_id[0x10];
11924 u8 reserved_at_60[0x20];
11928 u8 status[0x8];
11929 u8 reserved_at_8[0x18];
11931 u8 syndrome[0x20];
11933 u8 reserved_at_40[0x40];
11935 u8 required_umem_size[0x20];
11937 u8 reserved_at_a0[0x160];
11941 u8 opcode[0x10];
11942 u8 uid[0x10];
11944 u8 reserved_at_20[0x10];
11945 u8 op_mod[0x10];
11947 u8 reserved_at_40[0x10];
11948 u8 vhca_id[0x10];
11950 u8 reserved_at_60[0x20];
11952 u8 va[0x40];
11954 u8 mkey[0x20];
11956 u8 size[0x20];
11960 u8 status[0x8];
11961 u8 reserved_at_8[0x18];
11963 u8 syndrome[0x20];
11965 u8 actual_image_size[0x20];
11967 u8 reserved_at_60[0x20];
11971 u8 opcode[0x10];
11972 u8 uid[0x10];
11974 u8 reserved_at_20[0x10];
11975 u8 op_mod[0x10];
11977 u8 reserved_at_40[0x10];
11978 u8 vhca_id[0x10];
11980 u8 reserved_at_60[0x20];
11982 u8 va[0x40];
11984 u8 mkey[0x20];
11986 u8 size[0x20];
11990 u8 status[0x8];
11991 u8 reserved_at_8[0x18];
11993 u8 syndrome[0x20];
11995 u8 reserved_at_40[0x40];
11999 u8 reserved_at_0[0x3];
12000 u8 pg_track_log_max_num[0x5];
12001 u8 pg_track_max_num_range[0x8];
12002 u8 pg_track_log_min_addr_space[0x8];
12003 u8 pg_track_log_max_addr_space[0x8];
12005 u8 reserved_at_20[0x3];
12006 u8 pg_track_log_min_msg_size[0x5];
12007 u8 reserved_at_28[0x3];
12008 u8 pg_track_log_max_msg_size[0x5];
12009 u8 reserved_at_30[0x3];
12010 u8 pg_track_log_min_page_size[0x5];
12011 u8 reserved_at_38[0x3];
12012 u8 pg_track_log_max_page_size[0x5];
12014 u8 reserved_at_40[0x7c0];
12018 u8 dirty_address_high[0x20];
12020 u8 dirty_address_low[0x20];
12030 u8 start_address[0x40];
12032 u8 length[0x40];
12036 u8 modify_field_select[0x40];
12038 u8 reserved_at_40[0x10];
12039 u8 vhca_id[0x10];
12041 u8 reserved_at_60[0x20];
12043 u8 state[0x4];
12044 u8 track_type[0x4];
12045 u8 log_addr_space_size[0x8];
12046 u8 reserved_at_90[0x3];
12047 u8 log_page_size[0x5];
12048 u8 reserved_at_98[0x3];
12049 u8 log_msg_size[0x5];
12051 u8 reserved_at_a0[0x8];
12052 u8 reporting_qpn[0x18];
12054 u8 reserved_at_c0[0x18];
12055 u8 num_ranges[0x8];
12057 u8 reserved_at_e0[0x20];
12059 u8 range_start_address[0x40];
12061 u8 length[0x40];
12063 struct mlx5_ifc_page_track_range_bits track_range[0];