2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
14  *      - Redistributions of source code must retain the above
18  *      - Redistributions in binary form must reproduce the above
215 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
370 #define MLX5_24BIT_MASK		((1 << 24) - 1)
617 	struct mlx5_mpfs        *mpfs;  member
800 	struct mlx5_clock        clock;  member
893 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
899 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;  in fw_rev_maj()
904 	return ioread32be(&dev->iseg->fw_rev) >> 16;  in fw_rev_min()
909 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;  in fw_rev_sub()
927 	fbc->frags      = frags;  in mlx5_init_fbc_offset()
928 	fbc->log_stride = log_stride;  in mlx5_init_fbc_offset()
929 	fbc->log_sz     = log_sz;  in mlx5_init_fbc_offset()
930 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;  in mlx5_init_fbc_offset()
931 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;  in mlx5_init_fbc_offset()
932 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;  in mlx5_init_fbc_offset()
933 	fbc->strides_offset = strides_offset;  in mlx5_init_fbc_offset()
948 	ix  += fbc->strides_offset;  in mlx5_frag_buf_get_wqe()
949 	frag = ix >> fbc->log_frag_strides;  in mlx5_frag_buf_get_wqe()
951 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);  in mlx5_frag_buf_get_wqe()
957 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;  in mlx5_frag_buf_get_idx_last_contig_stride()
959 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);  in mlx5_frag_buf_get_idx_last_contig_stride()
1072 	return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);  in mlx5_db_alloc()
1125 /* Async-atomic event notifier used by mlx5 core to forward FW
1132 /* Async-atomic event notifier used for forwarding
1134  * eswitch, clock and others.
1197 	return dev->coredev_type == MLX5_COREDEV_PF;  in mlx5_core_is_pf()
1202 	return dev->coredev_type == MLX5_COREDEV_VF;  in mlx5_core_is_vf()
1207 	return dev->caps.embedded_cpu;  in mlx5_core_is_ecpf()
1213 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);  in mlx5_core_is_ecpf_esw_manager()
1223 	return dev->priv.sriov.max_vfs;  in mlx5_core_max_vfs()
1238 	return !!(dev->priv.rl_table.max_size);  in mlx5_rl_is_supported()
1271 		return idx - 1;  in mlx5_get_dev_index()
1273 		return PCI_FUNC(dev->pdev->devfn);  in mlx5_get_dev_index()
1287 	/* If RoCE cap is read-only in FW, get RoCE state from devlink  in mlx5_get_roce_state()