1172 /* Any new cap addition must update mlx5_hca_caps_alloc() to allocate
1202 	/* NUM OF CAP Types */
1234 #define MLX5_CAP_GEN(mdev, cap) \  argument
1235 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1237 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1238 	MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1240 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1241 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1243 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1244 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1246 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1247 	MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1249 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1250 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1252 #define MLX5_CAP_ETH(mdev, cap) \  argument
1254 		 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1256 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
1258 		 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->max, cap)
1260 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1262 		 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1264 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1265 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1267 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1268 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1270 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1271 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1273 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1274 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1276 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1277 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1279 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1280 	MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1282 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
1283 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->max, cap)
1285 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1286 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1288 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \  argument
1289 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1291 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1292 		MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1294 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \  argument
1295 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1297 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1298 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1300 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \  argument
1301 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1303 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1304 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1306 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \  argument
1307 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1309 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1310 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1312 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \  argument
1313 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
1315 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1316 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1318 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \  argument
1319 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap)
1321 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1323 		 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1325 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
1327 		 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->max, cap)
1329 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1330 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1332 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
1333 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1335 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1336 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1338 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1339 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1341 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1342 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1344 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1345 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1347 #define MLX5_CAP_ESW(mdev, cap) \  argument
1349 		 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1351 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1353 		(mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1355 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1357 		 mdev->caps.hca[MLX5_CAP_ESWITCH]->max, cap)
1359 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \  argument
1361 		 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap)
1363 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \  argument
1365 		 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
1367 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \  argument
1369 		 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1371 #define MLX5_CAP_ADV_VIRTUALIZATION_MAX(mdev, cap) \  argument
1373 		 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->max, cap)
1375 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \  argument
1376 	MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1378 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION_MAX(mdev, cap) \  argument
1379 	MLX5_CAP_PORT_SELECTION_MAX(mdev, flow_table_properties_port_selection.cap)
1381 #define MLX5_CAP_ODP(mdev, cap)\  argument
1382 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1384 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1385 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1387 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \  argument
1389 		 mdev->caps.hca[MLX5_CAP_VECTOR_CALC]->cur, cap)
1391 #define MLX5_CAP_QOS(mdev, cap)\  argument
1392 	MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1394 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1395 	MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1424 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1425 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1427 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1428 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1430 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1431 	MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1433 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1434 	MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1436 #define MLX5_CAP_TLS(mdev, cap) \  argument
1437 	MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1439 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1440 	MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1442 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1444 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1446 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1448 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1450 #define MLX5_CAP_IPSEC(mdev, cap)\  argument
1451 	MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1453 #define MLX5_CAP_DEV_SHAMPO(mdev, cap)\  argument
1454 	MLX5_GET(shampo_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_SHAMPO], cap)
1456 #define MLX5_CAP_MACSEC(mdev, cap)\  argument
1457 	MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)