Lines Matching +full:0 +full:x80
19 #define TPS65910 0
23 #define REGULATOR_LDO 0
31 #define TPS65910_SECONDS 0x0
32 #define TPS65910_MINUTES 0x1
33 #define TPS65910_HOURS 0x2
34 #define TPS65910_DAYS 0x3
35 #define TPS65910_MONTHS 0x4
36 #define TPS65910_YEARS 0x5
37 #define TPS65910_WEEKS 0x6
38 #define TPS65910_ALARM_SECONDS 0x8
39 #define TPS65910_ALARM_MINUTES 0x9
40 #define TPS65910_ALARM_HOURS 0xA
41 #define TPS65910_ALARM_DAYS 0xB
42 #define TPS65910_ALARM_MONTHS 0xC
43 #define TPS65910_ALARM_YEARS 0xD
44 #define TPS65910_RTC_CTRL 0x10
45 #define TPS65910_RTC_STATUS 0x11
46 #define TPS65910_RTC_INTERRUPTS 0x12
47 #define TPS65910_RTC_COMP_LSB 0x13
48 #define TPS65910_RTC_COMP_MSB 0x14
49 #define TPS65910_RTC_RES_PROG 0x15
50 #define TPS65910_RTC_RESET_STATUS 0x16
51 #define TPS65910_BCK1 0x17
52 #define TPS65910_BCK2 0x18
53 #define TPS65910_BCK3 0x19
54 #define TPS65910_BCK4 0x1A
55 #define TPS65910_BCK5 0x1B
56 #define TPS65910_PUADEN 0x1C
57 #define TPS65910_REF 0x1D
58 #define TPS65910_VRTC 0x1E
59 #define TPS65910_VIO 0x20
60 #define TPS65910_VDD1 0x21
61 #define TPS65910_VDD1_OP 0x22
62 #define TPS65910_VDD1_SR 0x23
63 #define TPS65910_VDD2 0x24
64 #define TPS65910_VDD2_OP 0x25
65 #define TPS65910_VDD2_SR 0x26
66 #define TPS65910_VDD3 0x27
67 #define TPS65910_VDIG1 0x30
68 #define TPS65910_VDIG2 0x31
69 #define TPS65910_VAUX1 0x32
70 #define TPS65910_VAUX2 0x33
71 #define TPS65910_VAUX33 0x34
72 #define TPS65910_VMMC 0x35
73 #define TPS65910_VPLL 0x36
74 #define TPS65910_VDAC 0x37
75 #define TPS65910_THERM 0x38
76 #define TPS65910_BBCH 0x39
77 #define TPS65910_DCDCCTRL 0x3E
78 #define TPS65910_DEVCTRL 0x3F
79 #define TPS65910_DEVCTRL2 0x40
80 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41
81 #define TPS65910_SLEEP_KEEP_RES_ON 0x42
82 #define TPS65910_SLEEP_SET_LDO_OFF 0x43
83 #define TPS65910_SLEEP_SET_RES_OFF 0x44
84 #define TPS65910_EN1_LDO_ASS 0x45
85 #define TPS65910_EN1_SMPS_ASS 0x46
86 #define TPS65910_EN2_LDO_ASS 0x47
87 #define TPS65910_EN2_SMPS_ASS 0x48
88 #define TPS65910_EN3_LDO_ASS 0x49
89 #define TPS65910_SPARE 0x4A
90 #define TPS65910_INT_STS 0x50
91 #define TPS65910_INT_MSK 0x51
92 #define TPS65910_INT_STS2 0x52
93 #define TPS65910_INT_MSK2 0x53
94 #define TPS65910_INT_STS3 0x54
95 #define TPS65910_INT_MSK3 0x55
96 #define TPS65910_GPIO0 0x60
97 #define TPS65910_GPIO1 0x61
98 #define TPS65910_GPIO2 0x62
99 #define TPS65910_GPIO3 0x63
100 #define TPS65910_GPIO4 0x64
101 #define TPS65910_GPIO5 0x65
102 #define TPS65910_GPIO6 0x66
103 #define TPS65910_GPIO7 0x67
104 #define TPS65910_GPIO8 0x68
105 #define TPS65910_JTAGVERNUM 0x80
106 #define TPS65910_MAX_REGISTER 0x80
111 #define TPS65911_VDDCTRL 0x27
112 #define TPS65911_VDDCTRL_OP 0x28
113 #define TPS65911_VDDCTRL_SR 0x29
114 #define TPS65911_LDO1 0x30
115 #define TPS65911_LDO2 0x31
116 #define TPS65911_LDO5 0x32
117 #define TPS65911_LDO8 0x33
118 #define TPS65911_LDO7 0x34
119 #define TPS65911_LDO6 0x35
120 #define TPS65911_LDO4 0x36
121 #define TPS65911_LDO3 0x37
122 #define TPS65911_VMBCH 0x6A
123 #define TPS65911_VMBCH2 0x6B
131 #define TPS65910_RTC_CTRL_STOP_RTC 0x01 /*0=stop, 1=run */
132 #define TPS65910_RTC_CTRL_AUTO_COMP 0x04
133 #define TPS65910_RTC_CTRL_GET_TIME 0x40
136 #define TPS65910_RTC_STATUS_ALARM 0x40
139 #define TPS65910_RTC_INTERRUPTS_EVERY 0x03
140 #define TPS65910_RTC_INTERRUPTS_IT_ALARM 0x08
142 /*Register BCK1 (0x80) register.RegisterDescription */
143 #define BCK1_BCKUP_MASK 0xFF
144 #define BCK1_BCKUP_SHIFT 0
147 /*Register BCK2 (0x80) register.RegisterDescription */
148 #define BCK2_BCKUP_MASK 0xFF
149 #define BCK2_BCKUP_SHIFT 0
152 /*Register BCK3 (0x80) register.RegisterDescription */
153 #define BCK3_BCKUP_MASK 0xFF
154 #define BCK3_BCKUP_SHIFT 0
157 /*Register BCK4 (0x80) register.RegisterDescription */
158 #define BCK4_BCKUP_MASK 0xFF
159 #define BCK4_BCKUP_SHIFT 0
162 /*Register BCK5 (0x80) register.RegisterDescription */
163 #define BCK5_BCKUP_MASK 0xFF
164 #define BCK5_BCKUP_SHIFT 0
167 /*Register PUADEN (0x80) register.RegisterDescription */
168 #define PUADEN_EN3P_MASK 0x80
170 #define PUADEN_I2CCTLP_MASK 0x40
172 #define PUADEN_I2CSRP_MASK 0x20
174 #define PUADEN_PWRONP_MASK 0x10
176 #define PUADEN_SLEEPP_MASK 0x08
178 #define PUADEN_PWRHOLDP_MASK 0x04
180 #define PUADEN_BOOT1P_MASK 0x02
182 #define PUADEN_BOOT0P_MASK 0x01
183 #define PUADEN_BOOT0P_SHIFT 0
186 /*Register REF (0x80) register.RegisterDescription */
187 #define REF_VMBCH_SEL_MASK 0x0C
189 #define REF_ST_MASK 0x03
190 #define REF_ST_SHIFT 0
193 /*Register VRTC (0x80) register.RegisterDescription */
194 #define VRTC_VRTC_OFFMASK_MASK 0x08
196 #define VRTC_ST_MASK 0x03
197 #define VRTC_ST_SHIFT 0
200 /*Register VIO (0x80) register.RegisterDescription */
201 #define VIO_ILMAX_MASK 0xC0
203 #define VIO_SEL_MASK 0x0C
205 #define VIO_ST_MASK 0x03
206 #define VIO_ST_SHIFT 0
209 /*Register VDD1 (0x80) register.RegisterDescription */
210 #define VDD1_VGAIN_SEL_MASK 0xC0
212 #define VDD1_ILMAX_MASK 0x20
214 #define VDD1_TSTEP_MASK 0x1C
216 #define VDD1_ST_MASK 0x03
217 #define VDD1_ST_SHIFT 0
220 /*Register VDD1_OP (0x80) register.RegisterDescription */
221 #define VDD1_OP_CMD_MASK 0x80
223 #define VDD1_OP_SEL_MASK 0x7F
224 #define VDD1_OP_SEL_SHIFT 0
227 /*Register VDD1_SR (0x80) register.RegisterDescription */
228 #define VDD1_SR_SEL_MASK 0x7F
229 #define VDD1_SR_SEL_SHIFT 0
232 /*Register VDD2 (0x80) register.RegisterDescription */
233 #define VDD2_VGAIN_SEL_MASK 0xC0
235 #define VDD2_ILMAX_MASK 0x20
237 #define VDD2_TSTEP_MASK 0x1C
239 #define VDD2_ST_MASK 0x03
240 #define VDD2_ST_SHIFT 0
243 /*Register VDD2_OP (0x80) register.RegisterDescription */
244 #define VDD2_OP_CMD_MASK 0x80
246 #define VDD2_OP_SEL_MASK 0x7F
247 #define VDD2_OP_SEL_SHIFT 0
249 /*Register VDD2_SR (0x80) register.RegisterDescription */
250 #define VDD2_SR_SEL_MASK 0x7F
251 #define VDD2_SR_SEL_SHIFT 0
261 /*Register VDD3 (0x80) register.RegisterDescription */
262 #define VDD3_CKINEN_MASK 0x04
264 #define VDD3_ST_MASK 0x03
265 #define VDD3_ST_SHIFT 0
269 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */
270 #define LDO_SEL_MASK 0x0C
272 #define LDO_ST_MASK 0x03
273 #define LDO_ST_SHIFT 0
274 #define LDO_ST_ON_BIT 0x01
275 #define LDO_ST_MODE_BIT 0x02
279 #define LDO1_SEL_MASK 0xFC
280 #define LDO3_SEL_MASK 0x7C
285 /*Register VDIG1 (0x80) register.RegisterDescription */
286 #define VDIG1_SEL_MASK 0x0C
288 #define VDIG1_ST_MASK 0x03
289 #define VDIG1_ST_SHIFT 0
292 /*Register VDIG2 (0x80) register.RegisterDescription */
293 #define VDIG2_SEL_MASK 0x0C
295 #define VDIG2_ST_MASK 0x03
296 #define VDIG2_ST_SHIFT 0
299 /*Register VAUX1 (0x80) register.RegisterDescription */
300 #define VAUX1_SEL_MASK 0x0C
302 #define VAUX1_ST_MASK 0x03
303 #define VAUX1_ST_SHIFT 0
306 /*Register VAUX2 (0x80) register.RegisterDescription */
307 #define VAUX2_SEL_MASK 0x0C
309 #define VAUX2_ST_MASK 0x03
310 #define VAUX2_ST_SHIFT 0
313 /*Register VAUX33 (0x80) register.RegisterDescription */
314 #define VAUX33_SEL_MASK 0x0C
316 #define VAUX33_ST_MASK 0x03
317 #define VAUX33_ST_SHIFT 0
320 /*Register VMMC (0x80) register.RegisterDescription */
321 #define VMMC_SEL_MASK 0x0C
323 #define VMMC_ST_MASK 0x03
324 #define VMMC_ST_SHIFT 0
327 /*Register VPLL (0x80) register.RegisterDescription */
328 #define VPLL_SEL_MASK 0x0C
330 #define VPLL_ST_MASK 0x03
331 #define VPLL_ST_SHIFT 0
334 /*Register VDAC (0x80) register.RegisterDescription */
335 #define VDAC_SEL_MASK 0x0C
337 #define VDAC_ST_MASK 0x03
338 #define VDAC_ST_SHIFT 0
341 /*Register THERM (0x80) register.RegisterDescription */
342 #define THERM_THERM_HD_MASK 0x20
344 #define THERM_THERM_TS_MASK 0x10
346 #define THERM_THERM_HDSEL_MASK 0x0C
348 #define THERM_RSVD1_MASK 0x02
350 #define THERM_THERM_STATE_MASK 0x01
351 #define THERM_THERM_STATE_SHIFT 0
354 /*Register BBCH (0x80) register.RegisterDescription */
355 #define BBCH_BBSEL_MASK 0x06
359 /*Register DCDCCTRL (0x80) register.RegisterDescription */
360 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20
362 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10
364 #define DCDCCTRL_VIO_PSKIP_MASK 0x08
366 #define DCDCCTRL_DCDCCKEXT_MASK 0x04
368 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03
369 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0
372 /*Register DEVCTRL (0x80) register.RegisterDescription */
373 #define DEVCTRL_PWR_OFF_MASK 0x80
375 #define DEVCTRL_RTC_PWDN_MASK 0x40
377 #define DEVCTRL_CK32K_CTRL_MASK 0x20
379 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10
381 #define DEVCTRL_DEV_OFF_RST_MASK 0x08
383 #define DEVCTRL_DEV_ON_MASK 0x04
385 #define DEVCTRL_DEV_SLP_MASK 0x02
387 #define DEVCTRL_DEV_OFF_MASK 0x01
388 #define DEVCTRL_DEV_OFF_SHIFT 0
391 /*Register DEVCTRL2 (0x80) register.RegisterDescription */
392 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30
394 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08
396 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04
398 #define DEVCTRL2_PWON_LP_RST_MASK 0x02
400 #define DEVCTRL2_IT_POL_MASK 0x01
401 #define DEVCTRL2_IT_POL_SHIFT 0
404 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */
405 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80
407 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40
409 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20
411 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10
413 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08
415 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04
417 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02
419 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01
420 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0
423 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */
424 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80
426 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40
428 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20
430 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10
432 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08
434 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04
436 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02
438 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01
439 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0
442 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */
443 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80
445 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40
447 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20
449 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10
451 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08
453 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04
455 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02
457 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01
458 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0
461 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */
462 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80
464 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60
466 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10
468 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08
470 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04
472 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02
474 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01
475 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0
478 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */
479 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80
481 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40
483 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20
485 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10
487 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08
489 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04
491 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02
493 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01
494 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0
497 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */
498 #define EN1_SMPS_ASS_RSVD_MASK 0xE0
500 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10
502 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08
504 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04
506 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02
508 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01
509 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0
512 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */
513 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80
515 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40
517 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20
519 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10
521 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08
523 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04
525 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02
527 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01
528 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0
531 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */
532 #define EN2_SMPS_ASS_RSVD_MASK 0xE0
534 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10
536 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08
538 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04
540 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02
542 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01
543 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0
546 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */
547 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80
549 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40
551 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20
553 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10
555 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08
557 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04
559 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02
561 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01
562 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0
565 /*Register SPARE (0x80) register.RegisterDescription */
566 #define SPARE_SPARE_MASK 0xFF
567 #define SPARE_SPARE_SHIFT 0
569 #define TPS65910_INT_STS_RTC_PERIOD_IT_MASK 0x80
571 #define TPS65910_INT_STS_RTC_ALARM_IT_MASK 0x40
573 #define TPS65910_INT_STS_HOTDIE_IT_MASK 0x20
575 #define TPS65910_INT_STS_PWRHOLD_F_IT_MASK 0x10
577 #define TPS65910_INT_STS_PWRON_LP_IT_MASK 0x08
579 #define TPS65910_INT_STS_PWRON_IT_MASK 0x04
581 #define TPS65910_INT_STS_VMBHI_IT_MASK 0x02
583 #define TPS65910_INT_STS_VMBDCH_IT_MASK 0x01
584 #define TPS65910_INT_STS_VMBDCH_IT_SHIFT 0
586 #define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
588 #define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
590 #define TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK 0x20
592 #define TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK 0x10
594 #define TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
596 #define TPS65910_INT_MSK_PWRON_IT_MSK_MASK 0x04
598 #define TPS65910_INT_MSK_VMBHI_IT_MSK_MASK 0x02
600 #define TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK 0x01
601 #define TPS65910_INT_MSK_VMBDCH_IT_MSK_SHIFT 0
604 #define TPS65910_INT_STS2_GPIO0_F_IT_MASK 0x02
606 #define TPS65910_INT_STS2_GPIO0_R_IT_MASK 0x01
609 #define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
611 #define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
613 /*Register INT_STS (0x80) register.RegisterDescription */
614 #define INT_STS_RTC_PERIOD_IT_MASK 0x80
616 #define INT_STS_RTC_ALARM_IT_MASK 0x40
618 #define INT_STS_HOTDIE_IT_MASK 0x20
620 #define INT_STS_PWRHOLD_R_IT_MASK 0x10
622 #define INT_STS_PWRON_LP_IT_MASK 0x08
624 #define INT_STS_PWRON_IT_MASK 0x04
626 #define INT_STS_VMBHI_IT_MASK 0x02
628 #define INT_STS_PWRHOLD_F_IT_MASK 0x01
629 #define INT_STS_PWRHOLD_F_IT_SHIFT 0
632 /*Register INT_MSK (0x80) register.RegisterDescription */
633 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
635 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
637 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20
639 #define INT_MSK_PWRHOLD_R_IT_MSK_MASK 0x10
641 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
643 #define INT_MSK_PWRON_IT_MSK_MASK 0x04
645 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02
647 #define INT_MSK_PWRHOLD_F_IT_MSK_MASK 0x01
648 #define INT_MSK_PWRHOLD_F_IT_MSK_SHIFT 0
651 /*Register INT_STS2 (0x80) register.RegisterDescription */
652 #define INT_STS2_GPIO3_F_IT_MASK 0x80
654 #define INT_STS2_GPIO3_R_IT_MASK 0x40
656 #define INT_STS2_GPIO2_F_IT_MASK 0x20
658 #define INT_STS2_GPIO2_R_IT_MASK 0x10
660 #define INT_STS2_GPIO1_F_IT_MASK 0x08
662 #define INT_STS2_GPIO1_R_IT_MASK 0x04
664 #define INT_STS2_GPIO0_F_IT_MASK 0x02
666 #define INT_STS2_GPIO0_R_IT_MASK 0x01
667 #define INT_STS2_GPIO0_R_IT_SHIFT 0
670 /*Register INT_MSK2 (0x80) register.RegisterDescription */
671 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80
673 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40
675 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20
677 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10
679 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08
681 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04
683 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
685 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
686 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0
689 /*Register INT_STS3 (0x80) register.RegisterDescription */
690 #define INT_STS3_PWRDN_IT_MASK 0x80
692 #define INT_STS3_VMBCH2_L_IT_MASK 0x40
694 #define INT_STS3_VMBCH2_H_IT_MASK 0x20
696 #define INT_STS3_WTCHDG_IT_MASK 0x10
698 #define INT_STS3_GPIO5_F_IT_MASK 0x08
700 #define INT_STS3_GPIO5_R_IT_MASK 0x04
702 #define INT_STS3_GPIO4_F_IT_MASK 0x02
704 #define INT_STS3_GPIO4_R_IT_MASK 0x01
705 #define INT_STS3_GPIO4_R_IT_SHIFT 0
708 /*Register INT_MSK3 (0x80) register.RegisterDescription */
709 #define INT_MSK3_PWRDN_IT_MSK_MASK 0x80
711 #define INT_MSK3_VMBCH2_L_IT_MSK_MASK 0x40
713 #define INT_MSK3_VMBCH2_H_IT_MSK_MASK 0x20
715 #define INT_MSK3_WTCHDG_IT_MSK_MASK 0x10
717 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08
719 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04
721 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02
723 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01
724 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0
727 /*Register GPIO (0x80) register.RegisterDescription */
728 #define GPIO_SLEEP_MASK 0x80
730 #define GPIO_DEB_MASK 0x10
732 #define GPIO_PUEN_MASK 0x08
734 #define GPIO_CFG_MASK 0x04
736 #define GPIO_STS_MASK 0x02
738 #define GPIO_SET_MASK 0x01
739 #define GPIO_SET_SHIFT 0
742 /*Register JTAGVERNUM (0x80) register.RegisterDescription */
743 #define JTAGVERNUM_VERNUM_MASK 0x0F
744 #define JTAGVERNUM_VERNUM_SHIFT 0
747 /* Register VDDCTRL (0x27) bit definitions */
748 #define VDDCTRL_ST_MASK 0x03
749 #define VDDCTRL_ST_SHIFT 0
752 /*Register VDDCTRL_OP (0x28) bit definitios */
753 #define VDDCTRL_OP_CMD_MASK 0x80
755 #define VDDCTRL_OP_SEL_MASK 0x7F
756 #define VDDCTRL_OP_SEL_SHIFT 0
759 /*Register VDDCTRL_SR (0x29) bit definitions */
760 #define VDDCTRL_SR_SEL_MASK 0x7F
761 #define VDDCTRL_SR_SEL_SHIFT 0
765 #define TPS65910_IRQ_VBAT_VMBDCH 0
777 #define TPS65911_IRQ_PWRHOLD_F 0
809 #define TPS65910_GPIO_SET BIT(0)
817 #define TPS65910_REG_VRTC 0
846 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 0x1
847 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 0x2
848 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 0x4
849 #define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP 0x8