Lines Matching full:19
110 #define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19)
112 #define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
229 #define IMX6Q_GPR4_SDMA_STOP_ACK BIT(19)
319 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK (0x1f << 19)
320 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I (0x10 << 19)
321 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M (0x10 << 19)
322 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X (0x1a << 19)
323 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I (0x12 << 19)
324 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M (0x12 << 19)
325 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X (0x1a << 19)
403 #define IMX6SX_GPR1_VADC_SW_RST_MASK (0x1 << 19)
404 #define IMX6SX_GPR1_VADC_SW_RST_RESET (0x1 << 19)
405 #define IMX6SX_GPR1_VADC_SW_RST_RELEASE (0x0 << 19)
434 #define IMX6SX_GPR5_PCIE_BTNRST_RESET BIT(19)
460 #define IMX6UL_GPR1_SAI1_MCLK_DIR (0x1 << 19)
463 #define IMX6UL_GPR1_SAI_MCLK_MASK (0x7 << 19)