Lines Matching full:comp
21 #define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
22 #define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
23 #define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
27 #define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
28 #define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
29 #define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
30 #define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
62 #define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
63 #define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
64 #define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
65 #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
66 #define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
67 #define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */
68 #define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
69 #define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */
70 #define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
71 #define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */