Lines Matching full:peripheral
204 #define APBREG_PWAC 0x20 /* Peripheral Write Access Control reg */
205 #define APBREG_PRAC 0x40 /* Peripheral Read Access Control reg */
206 #define APBREG_PCG 0x60 /* Peripheral Clock Gating Reg */
207 #define APBREG_PUR 0x80 /* Peripheral Under Reset Reg */
208 #define APBREG_EMU_PCG 0xA0 /* Emulator Peripheral Clock Gating Reg */
216 #define APBREG_PWAC_SARAC 0x120 /* Peripheral Write Access Control reg */
217 #define APBREG_PRAC_SARAC 0x140 /* Peripheral Read Access Control reg */
218 #define APBREG_PCG_SARAC 0x160 /* Peripheral Clock Gating Reg */
219 #define APBREG_PUR_SARAC 0x180 /* Peripheral Under Reset Reg */
220 #define APBREG_EMU_PCG_SARAC 0x1A0 /* Emulator Peripheral Clock Gating Reg */
260 #define SCTL_SCRESCTRL1 0x14 /* Peripheral reset control 1 */
261 #define SCTL_SCRESXTRL2 0x18 /* Peripheral reset control 2 */
262 #define SCTL_SCPEREN0 0x1c /* Peripheral clock enable register 0 */
263 #define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */
264 #define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */
265 #define SCTL_SCGRST 0x28 /* Peripheral global reset */
274 #define SCTL_SCCLKSTAT0 0x4c /* Peripheral clocks status 0 */
275 #define SCTL_SCCLKSTAT1 0x50 /* Peripheral clocks status 1 */
276 #define SCTL_SCCLKSTAT2 0x54 /* Peripheral clocks status 2 */