Lines Matching +full:interrupt +full:- +full:counter
1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2007-2009 Motorola, Inc.
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
31 #define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
32 #define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
33 #define CPCAP_REG_INTM1 0x0010 /* Interrupt Mask 1 */
34 #define CPCAP_REG_INTM2 0x0014 /* Interrupt Mask 2 */
35 #define CPCAP_REG_INTM3 0x0018 /* Interrupt Mask 3 */
36 #define CPCAP_REG_INTM4 0x001c /* Interrupt Mask 4 */
37 #define CPCAP_REG_INTS1 0x0020 /* Interrupt Sense 1 */
38 #define CPCAP_REG_INTS2 0x0024 /* Interrupt Sense 2 */
39 #define CPCAP_REG_INTS3 0x0028 /* Interrupt Sense 3 */
40 #define CPCAP_REG_INTS4 0x002c /* Interrupt Sense 4 */
50 #define CPCAP_REG_MI1 0x0200 /* Macro Interrupt 1 */
51 #define CPCAP_REG_MIM1 0x0204 /* Macro Interrupt Mask 1 */
52 #define CPCAP_REG_MI2 0x0208 /* Macro Interrupt 2 */
53 #define CPCAP_REG_MIM2 0x020c /* Macro Interrupt Mask 2 */
132 #define CPCAP_REG_CCC1 0x0a00 /* Coulomb Counter Control 1 */
135 #define CPCAP_REG_CCS1 0x0a0c /* Coulomb Counter Sample 1 */
136 #define CPCAP_REG_CCS2 0x0a10 /* Coulomb Counter Sample 2 */
137 #define CPCAP_REG_CCA1 0x0a14 /* Coulomb Counter Accumulator 1 */
138 #define CPCAP_REG_CCA2 0x0a18 /* Coulomb Counter Accumulator 2 */
139 #define CPCAP_REG_CCM 0x0a1c /* Coulomb Counter Mode */
140 #define CPCAP_REG_CCO 0x0a20 /* Coulomb Counter Offset */
141 #define CPCAP_REG_CCI 0x0a24 /* Coulomb Counter Integrator */
172 #define CPCAP_REG_UIER1 0x0e40 /* USB Interrupt Enable Rising 1 */
173 #define CPCAP_REG_UIER2 0x0e44 /* USB Interrupt Enable Rising 2 */
174 #define CPCAP_REG_UIER3 0x0e48 /* USB Interrupt Enable Rising 3 */
175 #define CPCAP_REG_UIEF1 0x0e4c /* USB Interrupt Enable Falling 1 */
176 #define CPCAP_REG_UIEF2 0x0e50 /* USB Interrupt Enable Falling 1 */
177 #define CPCAP_REG_UIEF3 0x0e54 /* USB Interrupt Enable Falling 1 */
178 #define CPCAP_REG_UIS 0x0e58 /* USB Interrupt Status */
179 #define CPCAP_REG_UIL 0x0e5c /* USB Interrupt Latch */
214 #define CPCAP_REG_OW1I 0x1208 /* One Wire 1 Interrupt */
215 #define CPCAP_REG_OW1IE 0x120c /* One Wire 1 Interrupt Enable */
221 #define CPCAP_REG_OW2I 0x1228 /* One Wire 2 Interrupt */
222 #define CPCAP_REG_OW2IE 0x122c /* One Wire 2 Interrupt Enable */
228 #define CPCAP_REG_OW3I 0x1248 /* One Wire 3 Interrupt */
229 #define CPCAP_REG_OW3IE 0x124c /* One Wire 3 Interrupt Enable */
235 #define CPCAP_REG_LGPU 0x1264 /* LMR GCAI GPIO Pull-up */