Lines Matching +full:sw +full:- +full:reset +full:- +full:number

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
27  * the number of GPIO in each register. We then need to multiply
39 #define ALTR_A10SR_LED_REG            0x02    /* LED - Upper 4 bits */
41 #define ALTR_A10SR_LED_VALID_SHIFT        4       /* LED - Upper 4 bits valid */
45 #define ALTR_A10SR_PBDSW_REG          0x04    /* PB & DIP SW - Input only */
46 #define ALTR_A10SR_PBDSW_IRQ_REG      0x06    /* PB & DIP SW Flag Clear */
55 #define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
56 #define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
60 #define ALTR_A10SR_WARM_RST_REG       0x1A    /* HPS Warm Reset */
61 #define ALTR_A10SR_WR_KEY_REG         0x1C    /* HPS Warm Reset Key */
65  * struct altr_a10sr - Altera Max5 MFD device private data structure