Lines Matching +full:0 +full:x2c
15 #define BLOCK_XG_MDIO_CSR_OFFSET 0x5000
16 #define BLOCK_DIAG_CSR_OFFSET 0xd000
17 #define XGENET_CONFIG_REG_ADDR 0x20
19 #define MAC_ADDR_REG_OFFSET 0x00
20 #define MAC_COMMAND_REG_OFFSET 0x04
21 #define MAC_WRITE_REG_OFFSET 0x08
22 #define MAC_READ_REG_OFFSET 0x0c
23 #define MAC_COMMAND_DONE_REG_OFFSET 0x10
25 #define CLKEN_OFFSET 0x08
26 #define SRST_OFFSET 0x00
28 #define MENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
29 #define MENET_BLOCK_MEM_RDY_ADDR 0x74
31 #define MAC_CONFIG_1_ADDR 0x00
32 #define MII_MGMT_COMMAND_ADDR 0x24
33 #define MII_MGMT_ADDRESS_ADDR 0x28
34 #define MII_MGMT_CONTROL_ADDR 0x2c
35 #define MII_MGMT_STATUS_ADDR 0x30
36 #define MII_MGMT_INDICATORS_ADDR 0x34
39 #define MII_MGMT_CONFIG_ADDR 0x20
40 #define MII_MGMT_COMMAND_ADDR 0x24
41 #define MII_MGMT_ADDRESS_ADDR 0x28
42 #define MII_MGMT_CONTROL_ADDR 0x2c
43 #define MII_MGMT_STATUS_ADDR 0x30
44 #define MII_MGMT_INDICATORS_ADDR 0x34
46 #define MIIM_COMMAND_ADDR 0x20
47 #define MIIM_FIELD_ADDR 0x24
48 #define MIIM_CONFIGURATION_ADDR 0x28
49 #define MIIM_LINKFAILVECTOR_ADDR 0x2c
50 #define MIIM_INDICATOR_ADDR 0x30
51 #define MIIMRD_FIELD_ADDR 0x34
53 #define MDIO_CSR_OFFSET 0x5000
55 #define REG_ADDR_POS 0
60 #define HSTMIIMWRDAT_POS 0
67 #define HSTMIIMCMD_POS 0
70 #define BUSY_MASK BIT(0)
71 #define READ_CYCLE_MASK BIT(0)