1 /* SPDX-License-Identifier: GPL-2.0 */
10  * Thanks. --rmk
36  * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
38  * IRQ_TYPE_NONE		- default, unspecified type
39  * IRQ_TYPE_EDGE_RISING		- rising edge triggered
40  * IRQ_TYPE_EDGE_FALLING	- falling edge triggered
41  * IRQ_TYPE_EDGE_BOTH		- rising and falling edge triggered
42  * IRQ_TYPE_LEVEL_HIGH		- high level triggered
43  * IRQ_TYPE_LEVEL_LOW		- low level triggered
44  * IRQ_TYPE_LEVEL_MASK		- Mask to filter out the level bits
45  * IRQ_TYPE_SENSE_MASK		- Mask for all the above bits
46  * IRQ_TYPE_DEFAULT		- For use by some PICs to ask irq_set_type
52  * IRQ_TYPE_PROBE		- Special flag for probing in progress
55  * IRQ_LEVEL			- Interrupt is level type. Will be also
58  * IRQ_PER_CPU			- Mark an interrupt PER_CPU. Will protect
59  *				  it from affinity setting
60  * IRQ_NOPROBE			- Interrupt cannot be probed by autoprobing
61  * IRQ_NOREQUEST		- Interrupt cannot be requested via
63  * IRQ_NOTHREAD			- Interrupt cannot be threaded
64  * IRQ_NOAUTOEN			- Interrupt is not automatically enabled in
66  * IRQ_NO_BALANCING		- Interrupt cannot be balanced (affinity set)
67  * IRQ_MOVE_PCNTXT		- Interrupt can be migrated from process context
68  * IRQ_NESTED_THREAD		- Interrupt nests into another thread
69  * IRQ_PER_CPU_DEVID		- Dev_id is a per-cpu variable
70  * IRQ_IS_POLLED		- Always polled by another interrupt. Exclude
71  *				  it from the spurious interrupt detection
73  * IRQ_DISABLE_UNLAZY		- Disable lazy irq disable
74  * IRQ_HIDDEN			- Don't show up in /proc/interrupts
75  * IRQ_NO_DEBUG			- Exclude from note_interrupt() debugging
115  * Return value for chip->irq_set_affinity()
117  * IRQ_SET_MASK_OK	- OK, core updates irq_common_data.affinity
118  * IRQ_SET_MASK_NOCPY	- OK, chip did update irq_common_data.affinity
119  * IRQ_SET_MASK_OK_DONE	- Same as IRQ_SET_MASK_OK for core. Special code to
133  * struct irq_common_data - per irq data shared by all irqchips
137  * @handler_data:	per-IRQ data for the irq_chip methods
138  * @affinity:		IRQ affinity on SMP. If this is an IPI
141  * @effective_affinity:	The effective IRQ affinity on SMP as some irq
143  *			A subset of @affinity.
145  * @ipi_offset:		Offset of first IPI target cpu in @affinity. Optional.
155 	cpumask_var_t		affinity;  member
166  * struct irq_data - per irq chip data passed down to chip functions
168  * @irq:		interrupt number
169  * @hwirq:		hardware interrupt number, local to the interrupt domain
171  * @chip:		low level interrupt hardware access
172  * @domain:		Interrupt translation domain; responsible for mapping
176  * @chip_data:		platform-specific per-chip private data for the chip
195  * IRQD_TRIGGER_MASK		- Mask for the trigger type bits
196  * IRQD_SETAFFINITY_PENDING	- Affinity setting is pending
197  * IRQD_ACTIVATED		- Interrupt has already been activated
198  * IRQD_NO_BALANCING		- Balancing disabled for this IRQ
199  * IRQD_PER_CPU			- Interrupt is per cpu
200  * IRQD_AFFINITY_SET		- Interrupt affinity was set
201  * IRQD_LEVEL			- Interrupt is level triggered
202  * IRQD_WAKEUP_STATE		- Interrupt is configured for wakeup
204  * IRQD_MOVE_PCNTXT		- Interrupt can be moved in process
206  * IRQD_IRQ_DISABLED		- Disabled state of the interrupt
207  * IRQD_IRQ_MASKED		- Masked state of the interrupt
208  * IRQD_IRQ_INPROGRESS		- In progress state of the interrupt
209  * IRQD_WAKEUP_ARMED		- Wakeup mode armed
210  * IRQD_FORWARDED_TO_VCPU	- The interrupt is forwarded to a VCPU
211  * IRQD_AFFINITY_MANAGED	- Affinity is auto-managed by the kernel
212  * IRQD_IRQ_STARTED		- Startup state of the interrupt
213  * IRQD_MANAGED_SHUTDOWN	- Interrupt was shutdown due to empty affinity
214  *				  mask. Applies only to affinity managed irqs.
215  * IRQD_SINGLE_TARGET		- IRQ allows only a single affinity target
216  * IRQD_DEFAULT_TRIGGER_SET	- Expected trigger already been set
217  * IRQD_CAN_RESERVE		- Can use reservation mode
218  * IRQD_MSI_NOMASK_QUIRK	- Non-maskable MSI quirk for affinity change
220  * IRQD_HANDLE_ENFORCE_IRQCTX	- Enforce that handle_irq_*() is only invoked
221  *				  from actual interrupt context.
222  * IRQD_AFFINITY_ON_ACTIVATE	- Affinity is set on activation. Don't call
224  * IRQD_IRQ_ENABLED_ON_SUSPEND	- Interrupt is enabled on suspend by irq pm if
254 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
455 	return d->hwirq;  in irqd_to_hwirq()
459  * struct irq_chip - hardware interrupt chip descriptor
462  * @irq_startup:	start up the interrupt (defaults to ->enable if NULL)
463  * @irq_shutdown:	shut down the interrupt (defaults to ->disable if NULL)
464  * @irq_enable:		enable the interrupt (defaults to chip->unmask if NULL)
465  * @irq_disable:	disable the interrupt
466  * @irq_ack:		start of a new interrupt
467  * @irq_mask:		mask an interrupt source
468  * @irq_mask_ack:	ack and mask an interrupt source
469  * @irq_unmask:		unmask an interrupt source
470  * @irq_eoi:		end of interrupt
471  * @irq_set_affinity:	Set the CPU affinity on SMP machines. If the force
473  *			unconditionally apply the affinity setting. Sanity
474  *			checks against the supplied affinity mask are not
479  * @irq_set_wake:	enable/disable power-management wake-on of an IRQ
482  * @irq_cpu_online:	configure an interrupt source for a secondary CPU
483  * @irq_cpu_offline:	un-configure an interrupt source for a secondary CPU
497  * @irq_get_irqchip_state:	return the internal state of an interrupt
498  * @irq_set_irqchip_state:	set the internal state of a interrupt
573  * IRQCHIP_AFFINITY_PRE_STARTUP:      Default affinity update before startup
594  * Pick up the arch-dependent methods:
654  * Built-in IRQ handlers for various IRQ types,
655  * callable via desc->handle_irq()
709 /* Checks whether the interrupt can be requested by request_irq(): */
712 /* Dummy irq-chip implementations: */
729 					  const struct cpumask *affinity);
731 					  struct cpumask *affinity);
823 	return d ? d->chip : NULL;  in irq_get_chip()
828 	return d->chip;  in irq_data_get_irq_chip()
834 	return d ? d->chip_data : NULL;  in irq_get_chip_data()
839 	return d->chip_data;  in irq_data_get_irq_chip_data()
845 	return d ? d->common->handler_data : NULL;  in irq_get_handler_data()
850 	return d->common->handler_data;  in irq_data_get_irq_handler_data()
856 	return d ? d->common->msi_desc : NULL;  in irq_get_msi_desc()
861 	return d->common->msi_desc;  in irq_data_get_msi_desc()
873 	return d->node;  in irq_common_data_get_node()
881 	return irq_common_data_get_node(d->common);  in irq_data_get_node()
888 	return d->common->affinity;  in irq_data_get_affinity_mask()
898 	cpumask_copy(d->common->affinity, m);  in irq_data_update_affinity()
913 	return d->common->effective_affinity;  in irq_data_get_effective_affinity_mask()
918 	cpumask_copy(d->common->effective_affinity, m);  in irq_data_update_effective_affinity()
944 		      const struct irq_affinity_desc *affinity);
948 			   const struct irq_affinity_desc *affinity);
955 	irq_alloc_descs(-1, 1, 1, node)
961 	irq_alloc_descs(-1, from, 1, node)
964 	irq_alloc_descs(-1, from, cnt, node)
970 	devm_irq_alloc_descs(dev, -1, 1, 1, node)
976 	devm_irq_alloc_descs(dev, -1, from, 1, node)
979 	devm_irq_alloc_descs(dev, -1, from, cnt, node)
992  * struct irq_chip_regs - register offsets for struct irq_gci
1012  * struct irq_chip_type - Generic interrupt chip instance for a flow type
1013  * @chip:		The real interrupt chip which provides the callbacks
1034  * struct irq_chip_generic - Generic irq chip data structure
1045  * @irq_base:		Interrupt base nr for this chip
1050  * @wake_enabled:	Interrupt can wakeup from suspend
1051  * @wake_active:	Interrupt is marked as an wakeup from suspend source
1058  * @chip_types:		Array of interrupt irq_chip_types
1090  * enum irq_gc_flags - Initialization flags for generic irq chips
1096  * @IRQ_GC_NO_MASK:		Do not calculate irq_data->mask
1097  * @IRQ_GC_BE_IO:		Use big-endian register accesses (default: LE)
1108  * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1114  * @gc:			Array of pointers to generic interrupt chips
1190 	return container_of(d->chip, struct irq_chip_type, chip);  in irq_data_get_chip_type()
1193 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1198 	raw_spin_lock(&gc->lock);  in irq_gc_lock()
1203 	raw_spin_unlock(&gc->lock);  in irq_gc_unlock()
1211  * The irqsave variants are for usage in non interrupt code. Do not use
1215 	raw_spin_lock_irqsave(&(gc)->lock, flags)
1218 	raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1223 	if (gc->reg_writel)  in irq_reg_writel()
1224 		gc->reg_writel(val, gc->reg_base + reg_offset);  in irq_reg_writel()
1226 		writel(val, gc->reg_base + reg_offset);  in irq_reg_writel()
1232 	if (gc->reg_readl)  in irq_reg_readl()
1233 		return gc->reg_readl(gc->reg_base + reg_offset);  in irq_reg_readl()
1235 		return readl(gc->reg_base + reg_offset);  in irq_reg_readl()
1271  * Registers a generic IRQ handling function as the top-level IRQ handler in
1273  * architecture-specific interrupt handler.
1275  * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1281  * Allows interrupt handlers to find the irqchip that's been registered as the
1282  * top-level IRQ handler.