Lines Matching +full:detector +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Power Management Controller (PMC) - System peripherals registers.
20 #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
39 #define AT91_PMC_PLL_CTRL0_ENPLL (1 << 28) /* Enable PLL */
40 #define AT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */
41 #define AT91_PMC_PLL_CTRL0_ENLOCK (1 << 31) /* Enable PLL lock */
45 #define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */
56 #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
57 #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
58 #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
59 #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
68 #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
71 #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
72 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
76 #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
99 #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
188 #define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
195 #define AT91_PMC_IER 0x60 /* Interrupt Enable Register */
209 #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
210 #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
218 #define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */
219 #define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */
220 #define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */
221 #define AT91_PMC_LPM BIT(20) /* Low-power Mode */
222 #define AT91_PMC_RXLP_MCE BIT(24) /* Backup UART Receive Enable */
223 #define AT91_PMC_ACC_CE BIT(25) /* ACC Enable */
232 #define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
242 #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
243 #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */
244 #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */
250 #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
251 #define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */