Lines Matching +full:clock +full:- +full:master
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Power Management Controller (PMC) - System peripherals registers.
20 #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
21 #define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
23 #define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
24 #define AT91_PMC_PCK (1 << 0) /* Processor Clock */
25 #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
26 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Susp…
27 #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
28 #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
29 #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
30 #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
31 #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
32 #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
33 #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
34 #define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */
35 #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
36 #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
40 #define AT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */
45 #define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */
46 #define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
47 #define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
55 #define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */
57 #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
59 #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
71 #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
72 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
76 #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
78 #define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */
79 #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
80 #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
84 #define AT91_PMC_RATIO 0x2c /* Processor clock ratio register [SAMA7G5 only] */
85 #define AT91_PMC_RATIO_RATIO (0xf) /* CPU clock ratio. */
90 #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
101 #define AT91_PMC_CPU_CKR 0x28 /* CPU Clock Register */
103 #define AT91_PMC_MCKR 0x30 /* Master Clock Register */
104 #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
111 #define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */
120 #define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate locati…
128 #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
138 #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
146 #define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */
174 #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
175 #define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
179 #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
183 #define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
184 #define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
185 #define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */
188 #define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
189 #define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate lengt…
191 #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
201 #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
204 #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
205 #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
206 #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
207 #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
209 #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
210 #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
212 #define AT91_PMC_MCKXRDY (1 << 26) /* Master Clock x [x=1..4] Ready Status */
221 #define AT91_PMC_LPM BIT(20) /* Low-power Mode */
242 #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
243 #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */
244 #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */