1 /* SPDX-License-Identifier: GPL-2.0 */
3  *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4  *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14  * top-level framework.  custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42  * struct clk_rate_request - Structure encoding the clk constraints that
75  * struct clk_duty - Struture encoding the duty cycle ratio of a clock
86  * struct clk_ops -  Callback operations for hardware clocks; these are to
134  *		0. Returns the calculated rate. Optional, but recommended - if
150  *		Returns 0 on success, -EERROR otherwise.
166  *		Returns 0 on success, -EERROR otherwise.
177  *		Returns 0 on success, -EERROR otherwise.
182  *		Returns the calculated accuracy.  Optional - if	this op is not
187  *		Returned values are 0-359 degrees on success, negative
190  * @set_phase:	Shift the phase this clock signal in degrees specified
192  *		0-359. Return 0 on success, otherwise -EERROR.
201  *              and >= numerator) Return 0 on success, otherwise -EERROR.
203  * @init:	Perform platform-specific initialization magic.
210  *		Returns 0 on success, -EERROR otherwise.
214  * @debug_init:	Set up type-specific debugfs entries for this clock.  This
218  *		prepare_lock held.  Returns 0 on success, -EERROR otherwise.
270  * struct clk_parent_data - clk parent information
284  * struct clk_init_data - holds init data that's common to all clocks and is
290  * @parent_data: array of parent data for all possible parents (when some
295  * @flags: framework-level hints and quirks
309  * struct clk_hw - handle for traversing from a struct clk to its corresponding
310  * hardware-specific structure.  struct clk_hw should be declared within struct
317  * @clk: pointer to the per-user struct clk instance that can be used to call
320  * @init: pointer to struct clk_init_data that contains the init data shared
340  * struct clk_fixed_rate - fixed-rate clock
341  * @hw:		handle between common and hardware-specific interfaces
347  * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
370  * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
375  * @flags: framework-specific flags
376  * @fixed_rate: non-adjustable clock rate
383  * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
388  * @flags: framework-specific flags
389  * @fixed_rate: non-adjustable clock rate
395  * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
400  * @flags: framework-specific flags
401  * @fixed_rate: non-adjustable clock rate
408  * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
412  * @parent_data: parent clk data
413  * @flags: framework-specific flags
414  * @fixed_rate: non-adjustable clock rate
422  * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
427  * @flags: framework-specific flags
428  * @fixed_rate: non-adjustable clock rate
429  * @fixed_accuracy: non-adjustable clock accuracy
438  * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
443  * @flags: framework-specific flags
444  * @fixed_rate: non-adjustable clock rate
445  * @fixed_accuracy: non-adjustable clock accuracy
453  * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
458  * @flags: framework-specific flags
459  * @fixed_rate: non-adjustable clock rate
460  * @fixed_accuracy: non-adjustable clock accuracy
468  * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
473  * @flags: framework-specific flags
474  * @fixed_rate: non-adjustable clock rate
488  * struct clk_gate - gating clock
490  * @hw:		handle between common and hardware-specific interfaces
493  * @flags:	hardware-specific flags
499  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
502  * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
503  *	of this register, and mask of gate bits are in higher 16-bit of this
504  *	register.  While setting the gate bits, higher 16-bit should also be
506  * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
544  * clk_hw_register_gate - register a gate clock with the clock framework
548  * @flags: framework-specific flags for this clock
551  * @clk_gate_flags: gate-specific flags for this clock
560  * clk_hw_register_gate_parent_hw - register a gate clock with the clock
565  * @flags: framework-specific flags for this clock
568  * @clk_gate_flags: gate-specific flags for this clock
577  * clk_hw_register_gate_parent_data - register a gate clock with the clock
581  * @parent_data: parent clk data
582  * @flags: framework-specific flags for this clock
585  * @clk_gate_flags: gate-specific flags for this clock
594  * devm_clk_hw_register_gate - register a gate clock with the clock framework
598  * @flags: framework-specific flags for this clock
601  * @clk_gate_flags: gate-specific flags for this clock
619  * struct clk_divider - adjustable divider clock
621  * @hw:		handle between common and hardware-specific interfaces
623  * @shift:	shift to the divider bit field
632  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
636  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
638  * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
643  * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
644  *	of this register, and mask of divider bits are in higher 16-bit of this
645  *	register.  While setting the divider bits, higher 16-bit should also be
647  * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
649  * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
651  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
654  * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
661 	u8		shift;  member
668 #define clk_div_mask(width)	((1 << (width)) - 1)
708 		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
714 		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
718 		void __iomem *reg, u8 shift, u8 width,
722  * clk_register_divider - register a divider clock with the clock framework
726  * @flags: framework-specific flags
728  * @shift: number of bits to shift the bitfield
730  * @clk_divider_flags: divider-specific flags for this clock
733 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \  argument
736 				   (reg), (shift), (width),		       \
739  * clk_hw_register_divider - register a divider clock with the clock framework
743  * @flags: framework-specific flags
745  * @shift: number of bits to shift the bitfield
747  * @clk_divider_flags: divider-specific flags for this clock
750 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift,    \  argument
753 				  NULL, (flags), (reg), (shift), (width),     \
756  * clk_hw_register_divider_parent_hw - register a divider clock with the clock
761  * @flags: framework-specific flags
763  * @shift: number of bits to shift the bitfield
765  * @clk_divider_flags: divider-specific flags for this clock
769 					  shift, width, clk_divider_flags,    \  argument
772 				  NULL, (flags), (reg), (shift), (width),     \
775  * clk_hw_register_divider_parent_data - register a divider clock with the clock
779  * @parent_data: parent clk data
780  * @flags: framework-specific flags
782  * @shift: number of bits to shift the bitfield
784  * @clk_divider_flags: divider-specific flags for this clock
788 					    reg, shift, width,		      \  argument
791 				  (parent_data), (flags), (reg), (shift),     \
794  * clk_hw_register_divider_table - register a table based divider clock with
799  * @flags: framework-specific flags
801  * @shift: number of bits to shift the bitfield
803  * @clk_divider_flags: divider-specific flags for this clock
808 				      shift, width, clk_divider_flags, table, \  argument
811 				  NULL, (flags), (reg), (shift), (width),     \
814  * clk_hw_register_divider_table_parent_hw - register a table based divider
819  * @flags: framework-specific flags
821  * @shift: number of bits to shift the bitfield
823  * @clk_divider_flags: divider-specific flags for this clock
828 						reg, shift, width,	      \  argument
832 				  NULL, (flags), (reg), (shift), (width),     \
835  * clk_hw_register_divider_table_parent_data - register a table based divider
839  * @parent_data: parent clk data
840  * @flags: framework-specific flags
842  * @shift: number of bits to shift the bitfield
844  * @clk_divider_flags: divider-specific flags for this clock
849 						  flags, reg, shift, width,   \  argument
853 				  (parent_data), (flags), (reg), (shift),     \
857  * devm_clk_hw_register_divider - register a divider clock with the clock framework
861  * @flags: framework-specific flags
863  * @shift: number of bits to shift the bitfield
865  * @clk_divider_flags: divider-specific flags for this clock
868 #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift,    \  argument
871 				  NULL, (flags), (reg), (shift), (width),     \
874  * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
878  * @flags: framework-specific flags
880  * @shift: number of bits to shift the bitfield
882  * @clk_divider_flags: divider-specific flags for this clock
886 					       reg, shift, width,	      \  argument
890 				       (shift), (width), (clk_divider_flags), \
893  * devm_clk_hw_register_divider_table - register a table based divider clock
898  * @flags: framework-specific flags
900  * @shift: number of bits to shift the bitfield
902  * @clk_divider_flags: divider-specific flags for this clock
907 					   reg, shift, width,		      \  argument
910 				       NULL, NULL, (flags), (reg), (shift),   \
918  * struct clk_mux - multiplexer clock
920  * @hw:		handle between common and hardware-specific interfaces
923  * @shift:	shift to multiplexer bit field
925  * @flags:	hardware-specific flags
932  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
933  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
934  * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
935  *	register, and mask of mux bits are in higher 16-bit of this register.
936  *	While setting the mux bits, higher 16-bit should also be updated to
938  * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
940  * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
942  * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
951 	u8		shift;  member
973 		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
980 		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
984 		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
988 			 shift, width, clk_mux_flags, lock)		      \  argument
990 			       (flags), (reg), (shift), BIT((width)) - 1,     \
993 				  flags, reg, shift, mask, clk_mux_flags,     \  argument
997 			      (shift), (mask), (clk_mux_flags), (table),      \
1000 				  num_parents, flags, reg, shift, mask,	      \  argument
1004 			      (shift), (mask), (clk_mux_flags), (table),      \
1007 			    shift, width, clk_mux_flags, lock)		      \  argument
1010 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
1013 				reg, shift, width, clk_mux_flags, lock)	      \  argument
1015 			      (parent_hws), NULL, (flags), (reg), (shift),    \
1016 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1018 					flags, reg, shift, width,	      \  argument
1021 			      (parent_data), (flags), (reg), (shift),	      \
1022 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1024 					      num_parents, flags, reg, shift, \  argument
1028 			      (parent_data), (flags), (reg), (shift),	      \
1029 			      BIT((width)) - 1, (clk_mux_flags), table, (lock))
1031 			    shift, width, clk_mux_flags, lock)		      \  argument
1034 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
1037 					    num_parents, flags, reg, shift,   \  argument
1041 				   (shift), BIT((width)) - 1,		      \
1044 					      num_parents, flags, reg, shift, \  argument
1048 			      NULL, (parent_data), (flags), (reg), (shift),   \
1049 			      BIT((width)) - 1, (clk_mux_flags), table, (lock))
1061  * struct clk_fixed_factor - fixed multiplier and divider clock
1063  * @hw:		handle between common and hardware-specific interfaces
1104  * struct clk_fractional_divider - adjustable fractional divider clock
1106  * @hw:		handle between common and hardware-specific interfaces
1108  * @mshift:	shift to the numerator bit field
1110  * @nshift:	shift to the denominator bit field
1117  * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1121  * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1124  * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1127  *	to shift left by a few bits in case, when the asked one is quite small
1129  *	caller's side the power-of-two capable prescaler exists.
1164  * struct clk_multiplier - adjustable multiplier clock
1166  * @hw:		handle between common and hardware-specific interfaces
1168  * @shift:	shift to the multiplier bit field
1176  * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1181  * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1183  * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1190 	u8		shift;  member
1205  * struct clk_composite - aggregate clock of mux, divider and gate clocks
1207  * @hw:		handle between common and hardware-specific interfaces
1208  * @mux_hw:	handle between composite and hardware-specific mux clock
1209  * @rate_hw:	handle between composite and hardware-specific rate clock
1210  * @gate_hw:	handle between composite and hardware-specific gate clock
1325 	dst->clk = src->clk;  in __clk_hw_set_clk()
1326 	dst->core = src->core;  in __clk_hw_set_clk()
1508 						   void *data),
1509 			void *data);
1512 						 void *data),
1513 			   void *data);
1516 						 void *data),
1517 			   void *data);
1521 				  void *data);
1523 				    void *data);
1524 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1526 				     void *data);
1536 						   void *data),  in of_clk_add_provider()  argument
1537 			void *data)  in of_clk_add_provider()
1543 					      void *data),  in of_clk_add_hw_provider()  argument
1544 			void *data)  in of_clk_add_hw_provider()
1550 						 void *data),  in devm_of_clk_add_hw_provider()  argument
1551 			   void *data)  in devm_of_clk_add_hw_provider()
1558 	struct of_phandle_args *clkspec, void *data)  in of_clk_src_simple_get()  argument
1560 	return ERR_PTR(-ENOENT);  in of_clk_src_simple_get()
1563 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)  in of_clk_hw_simple_get()  argument
1565 	return ERR_PTR(-ENOENT);  in of_clk_hw_simple_get()
1568 	struct of_phandle_args *clkspec, void *data)  in of_clk_src_onecell_get()  argument
1570 	return ERR_PTR(-ENOENT);  in of_clk_src_onecell_get()
1573 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)  in of_clk_hw_onecell_get()  argument
1575 	return ERR_PTR(-ENOENT);  in of_clk_hw_onecell_get()