Lines Matching +full:clock +full:- +full:accuracy
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
42 * struct clk_rate_request - Structure encoding the clk constraints that
43 * a clock user might require.
47 * @rate: Requested clock rate. This field will be adjusted by
48 * clock drivers according to hardware capabilities.
53 * @best_parent_hw: The most appropriate parent clock that fulfills the
75 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
86 * struct clk_ops - Callback operations for hardware clocks; these are to
87 * be provided by the clock implementation, and will be called by drivers
90 * @prepare: Prepare the clock for enabling. This must not return until
91 * the clock is fully prepared, and it's safe to call clk_enable.
92 * This callback is intended to allow clock implementations to
96 * @unprepare: Release the clock from its prepared state. This will typically
100 * @is_prepared: Queries the hardware to determine if the clock is prepared.
104 * @unprepare_unused: Unprepare the clock atomically. Only called from
108 * @enable: Enable the clock atomically. This must not return until the
109 * clock is generating a valid clock signal, usable by consumer
113 * @disable: Disable the clock atomically. Called with enable_lock held.
116 * @is_enabled: Queries the hardware to determine if the clock is enabled.
120 * @disable_unused: Disable the clock atomically. Only called from
125 * @save_context: Save the context of the clock in prepration for poweroff.
127 * @restore_context: Restore the context of the clock after a restoration
130 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
133 * driver cannot figure out a rate for this clock, it must return
134 * 0. Returns the calculated rate. Optional, but recommended - if
135 * this op is not set then clock rate will be initialized to 0.
138 * supported by the clock. The parent rate is an input/output
142 * actually supported by the clock, and optionally the parent clock
143 * that should be used to provide the clock rate.
145 * @set_parent: Change the input source of this clock; for clocks with multiple
150 * Returns 0 on success, -EERROR otherwise.
152 * @get_parent: Queries the hardware to determine the parent of a clock. The
154 * the parent clock. This index can be applied to either the
157 * index. Currently only called when the clock is initialized by
162 * @set_rate: Change the rate of this clock. The requested rate is specified
166 * Returns 0 on success, -EERROR otherwise.
168 * @set_rate_and_parent: Change the rate and the parent of this clock. The
177 * Returns 0 on success, -EERROR otherwise.
179 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
180 * is expressed in ppb (parts per billion). The parent accuracy is
182 * Returns the calculated accuracy. Optional - if this op is not
183 * set then clock accuracy will be initialized to parent accuracy
184 * or 0 (perfect clock) if clock has no parent.
186 * @get_phase: Queries the hardware to get the current phase of a clock.
187 * Returned values are 0-359 degrees on success, negative
190 * @set_phase: Shift the phase this clock signal in degrees specified
192 * 0-359. Return 0 on success, otherwise -EERROR.
195 * of a clock. Returned values denominator cannot be 0 and must be
198 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
201 * and >= numerator) Return 0 on success, otherwise -EERROR.
203 * @init: Perform platform-specific initialization magic.
204 * This is not used by any of the basic clock types.
207 * clock. It may also be used dynamic resource allocation is
208 * required. It shall not used to deal with clock parameters,
210 * Returns 0 on success, -EERROR otherwise.
214 * @debug_init: Set up type-specific debugfs entries for this clock. This
216 * clock has been created. The dentry pointer representing that
218 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
223 * (prepare) contexts. If enabling a clock requires code that might sleep,
224 * this must be done in clk_prepare. Clock enable code that will never be
227 * Typically, drivers will call clk_prepare when a clock may be needed later
228 * (eg. when a device is opened), and clk_enable when the clock is actually
270 * struct clk_parent_data - clk parent information
284 * struct clk_init_data - holds init data that's common to all clocks and is
285 * shared between the clock provider and the common clock framework.
287 * @name: clock name
288 * @ops: operations this clock supports
295 * @flags: framework-level hints and quirks
309 * struct clk_hw - handle for traversing from a struct clk to its corresponding
310 * hardware-specific structure. struct clk_hw should be declared within struct
317 * @clk: pointer to the per-user struct clk instance that can be used to call
321 * with the common clock framework. This pointer will be set to NULL once
331 * DOC: Basic clock implementations common to many platforms
333 * Each basic clock hardware type is comprised of a structure describing the
334 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
340 * struct clk_fixed_rate - fixed-rate clock
341 * @hw: handle between common and hardware-specific interfaces
342 * @fixed_rate: constant frequency of clock
343 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
347 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
370 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
372 * @dev: device that is registering this clock
373 * @name: name of this clock
374 * @parent_name: name of clock's parent
375 * @flags: framework-specific flags
376 * @fixed_rate: non-adjustable clock rate
383 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
385 * @dev: device that is registering this clock
386 * @name: name of this clock
387 * @parent_name: name of clock's parent
388 * @flags: framework-specific flags
389 * @fixed_rate: non-adjustable clock rate
395 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
396 * the clock framework
397 * @dev: device that is registering this clock
398 * @name: name of this clock
400 * @flags: framework-specific flags
401 * @fixed_rate: non-adjustable clock rate
408 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
409 * the clock framework
410 * @dev: device that is registering this clock
411 * @name: name of this clock
413 * @flags: framework-specific flags
414 * @fixed_rate: non-adjustable clock rate
422 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
423 * the clock framework
424 * @dev: device that is registering this clock
425 * @name: name of this clock
426 * @parent_name: name of clock's parent
427 * @flags: framework-specific flags
428 * @fixed_rate: non-adjustable clock rate
429 * @fixed_accuracy: non-adjustable clock accuracy
438 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
439 * clock with the clock framework
440 * @dev: device that is registering this clock
441 * @name: name of this clock
443 * @flags: framework-specific flags
444 * @fixed_rate: non-adjustable clock rate
445 * @fixed_accuracy: non-adjustable clock accuracy
453 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
454 * clock with the clock framework
455 * @dev: device that is registering this clock
456 * @name: name of this clock
457 * @parent_name: name of clock's parent
458 * @flags: framework-specific flags
459 * @fixed_rate: non-adjustable clock rate
460 * @fixed_accuracy: non-adjustable clock accuracy
468 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
469 * the clock framework
470 * @dev: device that is registering this clock
471 * @name: name of this clock
472 * @parent_name: name of clock's parent
473 * @flags: framework-specific flags
474 * @fixed_rate: non-adjustable clock rate
488 * struct clk_gate - gating clock
490 * @hw: handle between common and hardware-specific interfaces
493 * @flags: hardware-specific flags
496 * Clock which can gate its output. Implements .enable & .disable
499 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
500 * enable the clock. Setting this flag does the opposite: setting the bit
501 * disable the clock and clearing it enables the clock
502 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
503 * of this register, and mask of gate bits are in higher 16-bit of this
504 * register. While setting the gate bits, higher 16-bit should also be
506 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
544 * clk_hw_register_gate - register a gate clock with the clock framework
545 * @dev: device that is registering this clock
546 * @name: name of this clock
547 * @parent_name: name of this clock's parent
548 * @flags: framework-specific flags for this clock
549 * @reg: register address to control gating of this clock
550 * @bit_idx: which bit in the register controls gating of this clock
551 * @clk_gate_flags: gate-specific flags for this clock
552 * @lock: shared register lock for this clock
560 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
562 * @dev: device that is registering this clock
563 * @name: name of this clock
565 * @flags: framework-specific flags for this clock
566 * @reg: register address to control gating of this clock
567 * @bit_idx: which bit in the register controls gating of this clock
568 * @clk_gate_flags: gate-specific flags for this clock
569 * @lock: shared register lock for this clock
577 * clk_hw_register_gate_parent_data - register a gate clock with the clock
579 * @dev: device that is registering this clock
580 * @name: name of this clock
582 * @flags: framework-specific flags for this clock
583 * @reg: register address to control gating of this clock
584 * @bit_idx: which bit in the register controls gating of this clock
585 * @clk_gate_flags: gate-specific flags for this clock
586 * @lock: shared register lock for this clock
594 * devm_clk_hw_register_gate - register a gate clock with the clock framework
595 * @dev: device that is registering this clock
596 * @name: name of this clock
597 * @parent_name: name of this clock's parent
598 * @flags: framework-specific flags for this clock
599 * @reg: register address to control gating of this clock
600 * @bit_idx: which bit in the register controls gating of this clock
601 * @clk_gate_flags: gate-specific flags for this clock
602 * @lock: shared register lock for this clock
619 * struct clk_divider - adjustable divider clock
621 * @hw: handle between common and hardware-specific interfaces
628 * Clock with an adjustable divider affecting its output frequency. Implements
632 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
636 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
638 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
641 * zero divisor by not modifying their input clock
643 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
644 * of this register, and mask of divider bits are in higher 16-bit of this
645 * register. While setting the divider bits, higher 16-bit should also be
647 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
649 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
650 * not be changed by the clock framework.
651 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
654 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
668 #define clk_div_mask(width) ((1 << (width)) - 1)
722 * clk_register_divider - register a divider clock with the clock framework
723 * @dev: device registering this clock
724 * @name: name of this clock
725 * @parent_name: name of clock's parent
726 * @flags: framework-specific flags
730 * @clk_divider_flags: divider-specific flags for this clock
731 * @lock: shared register lock for this clock
739 * clk_hw_register_divider - register a divider clock with the clock framework
740 * @dev: device registering this clock
741 * @name: name of this clock
742 * @parent_name: name of clock's parent
743 * @flags: framework-specific flags
747 * @clk_divider_flags: divider-specific flags for this clock
748 * @lock: shared register lock for this clock
756 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
758 * @dev: device registering this clock
759 * @name: name of this clock
761 * @flags: framework-specific flags
765 * @clk_divider_flags: divider-specific flags for this clock
766 * @lock: shared register lock for this clock
775 * clk_hw_register_divider_parent_data - register a divider clock with the clock
777 * @dev: device registering this clock
778 * @name: name of this clock
780 * @flags: framework-specific flags
784 * @clk_divider_flags: divider-specific flags for this clock
785 * @lock: shared register lock for this clock
794 * clk_hw_register_divider_table - register a table based divider clock with
795 * the clock framework
796 * @dev: device registering this clock
797 * @name: name of this clock
798 * @parent_name: name of clock's parent
799 * @flags: framework-specific flags
803 * @clk_divider_flags: divider-specific flags for this clock
805 * @lock: shared register lock for this clock
814 * clk_hw_register_divider_table_parent_hw - register a table based divider
815 * clock with the clock framework
816 * @dev: device registering this clock
817 * @name: name of this clock
819 * @flags: framework-specific flags
823 * @clk_divider_flags: divider-specific flags for this clock
825 * @lock: shared register lock for this clock
835 * clk_hw_register_divider_table_parent_data - register a table based divider
836 * clock with the clock framework
837 * @dev: device registering this clock
838 * @name: name of this clock
840 * @flags: framework-specific flags
844 * @clk_divider_flags: divider-specific flags for this clock
846 * @lock: shared register lock for this clock
857 * devm_clk_hw_register_divider - register a divider clock with the clock framework
858 * @dev: device registering this clock
859 * @name: name of this clock
860 * @parent_name: name of clock's parent
861 * @flags: framework-specific flags
865 * @clk_divider_flags: divider-specific flags for this clock
866 * @lock: shared register lock for this clock
874 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
875 * @dev: device registering this clock
876 * @name: name of this clock
878 * @flags: framework-specific flags
882 * @clk_divider_flags: divider-specific flags for this clock
883 * @lock: shared register lock for this clock
893 * devm_clk_hw_register_divider_table - register a table based divider clock
894 * with the clock framework (devres variant)
895 * @dev: device registering this clock
896 * @name: name of this clock
897 * @parent_name: name of clock's parent
898 * @flags: framework-specific flags
902 * @clk_divider_flags: divider-specific flags for this clock
904 * @lock: shared register lock for this clock
918 * struct clk_mux - multiplexer clock
920 * @hw: handle between common and hardware-specific interfaces
925 * @flags: hardware-specific flags
928 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
932 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
933 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
934 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
935 * register, and mask of mux bits are in higher 16-bit of this register.
936 * While setting the mux bits, higher 16-bit should also be updated to
938 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
940 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
942 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
990 (flags), (reg), (shift), BIT((width)) - 1, \
1010 (shift), BIT((width)) - 1, (clk_mux_flags), \
1016 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1022 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1029 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1034 (shift), BIT((width)) - 1, (clk_mux_flags), \
1041 (shift), BIT((width)) - 1, \
1049 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1061 * struct clk_fixed_factor - fixed multiplier and divider clock
1063 * @hw: handle between common and hardware-specific interfaces
1067 * Clock with a fixed multiplier and divider. The output frequency is the
1068 * parent clock rate divided by div and multiplied by mult.
1104 * struct clk_fractional_divider - adjustable fractional divider clock
1106 * @hw: handle between common and hardware-specific interfaces
1114 * Clock with adjustable fractional divider affecting its output frequency.
1117 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1121 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1124 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1129 * caller's side the power-of-two capable prescaler exists.
1164 * struct clk_multiplier - adjustable multiplier clock
1166 * @hw: handle between common and hardware-specific interfaces
1172 * Clock with an adjustable multiplier affecting its output frequency.
1176 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1178 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1181 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1183 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1205 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1207 * @hw: handle between common and hardware-specific interfaces
1208 * @mux_hw: handle between composite and hardware-specific mux clock
1209 * @rate_hw: handle between composite and hardware-specific rate clock
1210 * @gate_hw: handle between composite and hardware-specific gate clock
1211 * @mux_ops: clock ops for mux
1212 * @rate_ops: clock ops for rate
1213 * @gate_ops: clock ops for gate
1325 dst->clk = src->clk; in __clk_hw_set_clk()
1326 dst->core = src->core; in __clk_hw_set_clk()
1350 * FIXME clock api without lock protection
1560 return ERR_PTR(-ENOENT); in of_clk_src_simple_get()
1565 return ERR_PTR(-ENOENT); in of_clk_hw_simple_get()
1570 return ERR_PTR(-ENOENT); in of_clk_src_onecell_get()
1575 return ERR_PTR(-ENOENT); in of_clk_hw_onecell_get()