Lines Matching +full:tx +full:- +full:output +full:- +full:config
1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
13 #define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
57 #define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
58 #define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
81 #define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
86 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
87 #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
88 #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
89 #define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
137 #define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
138 #define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
139 #define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
172 /* PCIE Config space accessing MACROS */
237 #define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
238 #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
239 #define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
240 #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
256 return -ENOTSUPP; in bcma_core_pci_pcibios_map_irq()
260 return -ENOTSUPP; in bcma_core_pci_plat_dev_init()