Lines Matching full:27
30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
364 #define M4U_PORT_L27_CAM_IMGO_R1 MTK_M4U_ID(27, 0)
365 #define M4U_PORT_L27_CAM_CQI_R1 MTK_M4U_ID(27, 1)
366 #define M4U_PORT_L27_CAM_CQI_R2 MTK_M4U_ID(27, 2)
367 #define M4U_PORT_L27_CAM_BPCI_R1 MTK_M4U_ID(27, 3)
368 #define M4U_PORT_L27_CAM_LSCI_R1 MTK_M4U_ID(27, 4)
369 #define M4U_PORT_L27_CAM_RAWI_R2 MTK_M4U_ID(27, 5)
370 #define M4U_PORT_L27_CAM_RAWI_R3 MTK_M4U_ID(27, 6)
371 #define M4U_PORT_L27_CAM_UFDI_R2 MTK_M4U_ID(27, 7)
372 #define M4U_PORT_L27_CAM_UFDI_R3 MTK_M4U_ID(27, 8)
373 #define M4U_PORT_L27_CAM_RAWI_R4 MTK_M4U_ID(27, 9)
374 #define M4U_PORT_L27_CAM_RAWI_R5 MTK_M4U_ID(27, 10)
375 #define M4U_PORT_L27_CAM_AAI_R1 MTK_M4U_ID(27, 11)
376 #define M4U_PORT_L27_CAM_FHO_R1 MTK_M4U_ID(27, 12)
377 #define M4U_PORT_L27_CAM_AAO_R1 MTK_M4U_ID(27, 13)
378 #define M4U_PORT_L27_CAM_TSFSO_R1 MTK_M4U_ID(27, 14)
379 #define M4U_PORT_L27_CAM_FLKO_R1 MTK_M4U_ID(27, 15)
402 #define IOMMU_PORT_INFRA_SSUSB_P1_0_W MTK_IFAIOMMU_PERI_ID(27)