Lines Matching full:19
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
119 #define M4U_PORT_L9_IMG_SMTO_T1_B MTK_M4U_ID(9, 19)
141 #define M4U_PORT_L10_IMG_IMG2O_D1_A MTK_M4U_ID(10, 19)
236 #define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(19, 0)
237 #define M4U_PORT_L19_VENC_REC MTK_M4U_ID(19, 1)
238 #define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(19, 2)
239 #define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(19, 3)
240 #define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(19, 4)
241 #define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(19, 5)
242 #define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(19, 6)
243 #define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(19, 7)
244 #define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(19, 8)
245 #define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(19, 9)
246 #define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(19, 10)
247 #define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(19, 11)
248 #define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(19, 12)
249 #define M4U_PORT_L19_JPGDEC_WDMA0 MTK_M4U_ID(19, 13)
250 #define M4U_PORT_L19_JPGDEC_BSDMA0 MTK_M4U_ID(19, 14)
251 #define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(19, 15)
252 #define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(19, 16)
253 #define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(19, 17)
254 #define M4U_PORT_L19_JPGDEC_WDMA1 MTK_M4U_ID(19, 18)
255 #define M4U_PORT_L19_JPGDEC_BSDMA1 MTK_M4U_ID(19, 19)
256 #define M4U_PORT_L19_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(19, 20)
257 #define M4U_PORT_L19_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(19, 21)
258 #define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(19, 22)
259 #define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(19, 23)
260 #define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(19, 24)
261 #define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(19, 25)
262 #define M4U_PORT_L19_VENC_SUB_R_CHROMA MTK_M4U_ID(19, 26)
284 #define M4U_PORT_L20_JPGDEC_BSDMA1 MTK_M4U_ID(20, 19)