Lines Matching +full:0 +full:- +full:9
1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
13 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
20 * modules dma-address-region larbs-ports
21 * disp 0 ~ 4G larb0/1/2/3
25 * CCU0 0x24000_0000 ~ 0x243ff_ffff larb18: port 0/1
26 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb18: port 2/3
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
35 #define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 0)
36 #define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 1)
37 #define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(0, 2)
38 #define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(0, 3)
39 #define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(0, 4)
40 #define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5)
43 #define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 0)
51 #define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0)
58 #define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(3, 0)
67 #define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(4, 0)
74 #define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(5, 0)
84 #define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(6, 0)
90 #define M4U_PORT_L7_IMG_WPE_RDMA0 MTK_M4U_ID(7, 0)
95 #define M4U_PORT_L8_IMG_WPE_RDMA0 MTK_M4U_ID(8, 0)
100 #define M4U_PORT_L9_IMG_IMGI_T1_A MTK_M4U_ID(9, 0)
101 #define M4U_PORT_L9_IMG_IMGBI_T1_A MTK_M4U_ID(9, 1)
102 #define M4U_PORT_L9_IMG_IMGCI_T1_A MTK_M4U_ID(9, 2)
103 #define M4U_PORT_L9_IMG_SMTI_T1_A MTK_M4U_ID(9, 3)
104 #define M4U_PORT_L9_IMG_TNCSTI_T1_A MTK_M4U_ID(9, 4)
105 #define M4U_PORT_L9_IMG_TNCSTI_T4_A MTK_M4U_ID(9, 5)
106 #define M4U_PORT_L9_IMG_YUVO_T1_A MTK_M4U_ID(9, 6)
107 #define M4U_PORT_L9_IMG_TIMGO_T1_A MTK_M4U_ID(9, 7)
108 #define M4U_PORT_L9_IMG_YUVO_T2_A MTK_M4U_ID(9, 8)
109 #define M4U_PORT_L9_IMG_IMGI_T1_B MTK_M4U_ID(9, 9)
110 #define M4U_PORT_L9_IMG_IMGBI_T1_B MTK_M4U_ID(9, 10)
111 #define M4U_PORT_L9_IMG_IMGCI_T1_B MTK_M4U_ID(9, 11)
112 #define M4U_PORT_L9_IMG_YUVO_T5_A MTK_M4U_ID(9, 12)
113 #define M4U_PORT_L9_IMG_SMTI_T1_B MTK_M4U_ID(9, 13)
114 #define M4U_PORT_L9_IMG_TNCSO_T1_A MTK_M4U_ID(9, 14)
115 #define M4U_PORT_L9_IMG_SMTO_T1_A MTK_M4U_ID(9, 15)
116 #define M4U_PORT_L9_IMG_TNCSTO_T1_A MTK_M4U_ID(9, 16)
117 #define M4U_PORT_L9_IMG_YUVO_T2_B MTK_M4U_ID(9, 17)
118 #define M4U_PORT_L9_IMG_YUVO_T5_B MTK_M4U_ID(9, 18)
119 #define M4U_PORT_L9_IMG_SMTO_T1_B MTK_M4U_ID(9, 19)
122 #define M4U_PORT_L10_IMG_IMGI_D1_A MTK_M4U_ID(10, 0)
131 #define M4U_PORT_L10_IMG_PIMGI_P1_A MTK_M4U_ID(10, 9)
148 #define M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A MTK_M4U_ID(11, 0)
157 #define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A MTK_M4U_ID(11, 9)
160 #define M4U_PORT_L12_IMG_FDVT_RDA MTK_M4U_ID(12, 0)
169 #define M4U_PORT_L12_IMG_DVP_WDMA MTK_M4U_ID(12, 9)
172 #define M4U_PORT_L13_CAM_CAMSV_CQI_E1 MTK_M4U_ID(13, 0)
181 #define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 9)
184 #define M4U_PORT_L14_CAM_GCAMSV_A_IMGO_1 MTK_M4U_ID(14, 0)
193 #define M4U_PORT_L14_CAM_IPU2O MTK_M4U_ID(14, 9)
203 #define M4U_PORT_L16_CAM_IMGO_R1 MTK_M4U_ID(16, 0)
212 #define M4U_PORT_L16_CAM_RAWI_R4 MTK_M4U_ID(16, 9)
221 #define M4U_PORT_L17_CAM_YUVO_R1 MTK_M4U_ID(17, 0)
230 #define M4U_PORT_L18_CAM_CCUI MTK_M4U_ID(18, 0)
236 #define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(19, 0)
245 #define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(19, 9)
265 #define M4U_PORT_L20_VENC_RCPU MTK_M4U_ID(20, 0)
274 #define M4U_PORT_L20_JPGENC_Q_TABLE MTK_M4U_ID(20, 9)
294 #define M4U_PORT_L21_VDEC_MC_EXT MTK_M4U_ID(21, 0)
303 #define M4U_PORT_L21_VDEC_AVC_MV_EXT MTK_M4U_ID(21, 9)
306 #define M4U_PORT_L22_VDEC_MC_EXT MTK_M4U_ID(22, 0)
315 #define M4U_PORT_L22_VDEC_AVC_MV_EXT MTK_M4U_ID(22, 9)
318 #define M4U_PORT_L23_VDEC_UFO_ENC_EXT MTK_M4U_ID(23, 0)
322 #define M4U_PORT_L24_VDEC_LAT0_VLD_EXT MTK_M4U_ID(24, 0)
331 #define M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT MTK_M4U_ID(24, 9)
336 #define M4U_PORT_L25_CAM_MRAW0_LSCI_M1 MTK_M4U_ID(25, 0)
345 #define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1 MTK_M4U_ID(25, 9)
350 #define M4U_PORT_L26_CAM_MRAW1_LSCI_M1 MTK_M4U_ID(26, 0)
359 #define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1 MTK_M4U_ID(26, 9)
364 #define M4U_PORT_L27_CAM_IMGO_R1 MTK_M4U_ID(27, 0)
373 #define M4U_PORT_L27_CAM_RAWI_R4 MTK_M4U_ID(27, 9)
382 #define M4U_PORT_L28_CAM_YUVO_R1 MTK_M4U_ID(28, 0)