Lines Matching +full:- +full:2 +full:g

1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
15  * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18  * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
22  * modules    dma-address-region	larbs-ports
23  * disp         0 ~ 4G                  larb0/1/2
24  * vcodec      4G ~ 8G                  larb4/7
25  * cam/mdp     8G ~ 12G                 the other larbs.
26  * N/A         12G ~ 16G
32 /* LARB 0 -- MMSYS */
35 #define IOMMU_PORT_L0_OVL_RDMA0		MTK_M4U_ID(0, 2)
38 /* LARB 1 -- MMSYS */
41 #define IOMMU_PORT_L1_DISP_RDMA0	MTK_M4U_ID(1, 2)
45 /* LARB 2 -- MMSYS */
46 #define IOMMU_PORT_L2_MDP_RDMA0		MTK_M4U_ID(2, 0)
47 #define IOMMU_PORT_L2_MDP_RDMA1		MTK_M4U_ID(2, 1)
48 #define IOMMU_PORT_L2_MDP_WROT0		MTK_M4U_ID(2, 2)
49 #define IOMMU_PORT_L2_MDP_WROT1		MTK_M4U_ID(2, 3)
50 #define IOMMU_PORT_L2_DISP_FAKE0	MTK_M4U_ID(2, 4)
52 /* LARB 4 -- VDEC */
55 #define IOMMU_PORT_L4_HW_VDEC_PP_EXT		MTK_M4U_ID(4, 2)
68 /* LARB 7 -- VENC */
71 #define IOMMU_PORT_L7_VENC_BSDMA	MTK_M4U_ID(7, 2)
83 /* LARB 8 -- WPE */
86 #define IOMMU_PORT_L8_WPE_WDMA_0	MTK_M4U_ID(8, 2)
88 /* LARB 9 -- IMG-1 */
91 #define IOMMU_PORT_L9_IMG_DMGI_D1	MTK_M4U_ID(9, 2)
119 /* LARB 11 -- IMG-2 */
122 #define IOMMU_PORT_L11_IMG_DMGI_D1	MTK_M4U_ID(11, 2)
150 /* LARB 13 -- CAM */
153 #define IOMMU_PORT_L13_CAM_MRAWO_1	MTK_M4U_ID(13, 2)
161 /* LARB 14 -- CAM */
165 /* LARB 16 -- RAW-A */
168 #define IOMMU_PORT_L16_CAM_CQI_R1_A	MTK_M4U_ID(16, 2)
184 /* LARB 17 -- RAW-B */
187 #define IOMMU_PORT_L17_CAM_CQI_R1_B	MTK_M4U_ID(17, 2)
203 /* LARB 19 -- IPE */
206 #define IOMMU_PORT_L19_IPE_DVP_RDMA	MTK_M4U_ID(19, 2)
209 /* LARB 20 -- IPE */
212 #define IOMMU_PORT_L20_IPE_FDVT_WRA	MTK_M4U_ID(20, 2)