Lines Matching full:divider

89 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
147 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */
149 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */
151 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */
153 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */
155 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
207 /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
209 /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
211 /** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */
221 /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
225 /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
227 /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
229 /** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */
237 /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
241 /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
243 /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
245 /** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */
253 /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
257 /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
259 /** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */
261 /** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */
271 /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */
273 /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */