Lines Matching full:output

12 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
14 /** @brief output of gate CLK_ENB_APB2APE */
16 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
18 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
20 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
22 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
24 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
26 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
28 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
30 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
41 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
43 /** @brief output of gate CLK_ENB_FUSE */
45 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
47 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
49 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
51 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
53 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
55 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
57 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
59 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
61 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
65 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
69 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
73 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
77 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
81 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */
87 /** @brief PLLP clk output */
89 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
91 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
93 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
95 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
97 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
99 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
101 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
103 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
105 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
107 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
109 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
111 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
113 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
115 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
117 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
119 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
121 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
123 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
125 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
127 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
129 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
131 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
133 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
135 /** @brief output of gate CLK_ENB_PEX1_CORE_6 */
137 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
139 /** @brief output of gate CLK_ENB_PEX2_CORE_7 */
141 /** @brief output of gate CLK_ENB_PEX2_CORE_8 */
143 /** @brief output of gate CLK_ENB_PEX2_CORE_9 */
145 /** @brief output of gate CLK_ENB_PEX2_CORE_10 */
147 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */
149 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */
151 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */
153 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */
155 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
157 /** @brief output of gate CLK_ENB_PEX0_CORE_0 */
159 /** @brief output of gate CLK_ENB_PEX0_CORE_1 */
161 /** @brief output of gate CLK_ENB_PEX0_CORE_2 */
163 /** @brief output of gate CLK_ENB_PEX0_CORE_3 */
165 /** @brief output of gate CLK_ENB_PEX0_CORE_4 */
167 /** @brief output of gate CLK_ENB_PEX1_CORE_5 */
189 /** @brief Monitored branch of MGBE0 RX PCS mux output */
191 /** @brief Monitored branch of MGBE1 RX PCS mux output */
193 /** @brief Monitored branch of MGBE2 RX PCS mux output */
195 /** @brief Monitored branch of MGBE3 RX PCS mux output */
205 /** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */
207 /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
209 /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
211 /** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */
213 /** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */
215 /** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */
217 /** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */
219 /** @brief GBE_UPHY_MGBE0_APP_CLK gate output */
221 /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
223 /** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */
225 /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
227 /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
229 /** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */
231 /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */
233 /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */
235 /** @brief GBE_UPHY_MGBE1_APP_CLK gate output */
237 /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
239 /** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */
241 /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
243 /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
245 /** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */
247 /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */
249 /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */
251 /** @brief GBE_UPHY_MGBE2_APP_CLK gate output */
253 /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
255 /** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */
257 /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
259 /** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */
261 /** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */
263 /** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */
265 /** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */
267 /** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */
269 /** @brief GBE_UPHY_MGBE3_APP_CLK gate output */
271 /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */
273 /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */